/dports/devel/distorm/distorm-20121220-r230/src/ |
H A D | insts.c | 35 _InstInfo II_PAUSE = /*II*/ {0x88, 10021}; variable
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H A D | insts.h | 57 extern _InstInfo II_PAUSE;
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H A D | instructions.c | 399 return &II_PAUSE; in inst_lookup()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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H A D | MicroMipsInstrInfo.td | 1086 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 159 def II_PAUSE : InstrItinClass; 552 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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H A D | MicroMipsInstrInfo.td | 1086 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 160 def II_PAUSE : InstrItinClass; 554 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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H A D | MicroMipsInstrInfo.td | 1086 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 159 def II_PAUSE : InstrItinClass; 552 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 160 def II_PAUSE : InstrItinClass; 554 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 159 def II_PAUSE : InstrItinClass; 552 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsSchedule.td | 161 def II_PAUSE : InstrItinClass; 557 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 159 def II_PAUSE : InstrItinClass; 552 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 160 def II_PAUSE : InstrItinClass; 553 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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H A D | MipsScheduleGeneric.td | 222 def : ItinRW<[GenericWriteCOP0], [II_EHB, II_PAUSE, II_WAIT]>;
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Mips/ |
H A D | MipsSchedule.td | 159 def II_PAUSE : InstrItinClass; 551 InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
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H A D | MipsScheduleGeneric.td | 222 def : ItinRW<[GenericWriteCOP0], [II_EHB, II_PAUSE, II_WAIT]>;
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