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Searched refs:INVALID_REG (Results 1 – 25 of 261) sorted by relevance

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/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/Core/MIPS/ARM64/
H A DArm64RegCache.cpp52 mr[i].reg = INVALID_REG; in Start()
265 return INVALID_REG; in AllocateReg()
305 return INVALID_REG; in FindBestToSpill()
328 return INVALID_REG; in TryMapTempImm()
344 return INVALID_REG; in MapReg()
349 return INVALID_REG; in MapReg()
601 return INVALID_REG; in ARM64RegForFlush()
619 return INVALID_REG; in ARM64RegForFlush()
622 return INVALID_REG; in ARM64RegForFlush()
626 return INVALID_REG; in ARM64RegForFlush()
[all …]
H A DArm64RegCacheFPU.cpp61 mrInitial[i].reg = INVALID_REG;
179 return INVALID_REG;
333 mr[r].reg = (int)INVALID_REG;
342 return INVALID_REG;
347 return INVALID_REG;
351 return INVALID_REG;
356 return INVALID_REG;
360 return INVALID_REG;
388 if (ar1 != INVALID_REG && ar2 != INVALID_REG) {
459 mr[r].reg = (int)INVALID_REG;
[all …]
H A DArm64CompLoadStore.cpp156 ANDI2R(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift, INVALID_REG); in Comp_ITypeMemLR()
168 ANDI2R(SCRATCH2, SCRATCH2, 0xffffff00 << shift, INVALID_REG); in Comp_ITypeMemLR()
175 ANDI2R(SCRATCH2, SCRATCH2, 0x00ffffff >> (24 - shift), INVALID_REG); in Comp_ITypeMemLR()
282 ARM64Reg targetReg = INVALID_REG; in Comp_ITypeMem()
283 ARM64Reg addrReg = INVALID_REG; in Comp_ITypeMem()
326 targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt); in Comp_ITypeMem()
327 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
349 if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) { in Comp_ITypeMem()
368 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
375 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
[all …]
/dports/emulators/ppsspp/ppsspp-1.12.3/Core/MIPS/ARM64/
H A DArm64RegCache.cpp52 mr[i].reg = INVALID_REG; in Start()
265 return INVALID_REG; in AllocateReg()
305 return INVALID_REG; in FindBestToSpill()
328 return INVALID_REG; in TryMapTempImm()
344 return INVALID_REG; in MapReg()
349 return INVALID_REG; in MapReg()
601 return INVALID_REG; in ARM64RegForFlush()
619 return INVALID_REG; in ARM64RegForFlush()
622 return INVALID_REG; in ARM64RegForFlush()
626 return INVALID_REG; in ARM64RegForFlush()
[all …]
H A DArm64RegCacheFPU.cpp61 mrInitial[i].reg = INVALID_REG; in SetupInitialRegs()
179 return INVALID_REG; in MapReg()
333 mr[r].reg = (int)INVALID_REG; in FlushR()
342 return INVALID_REG; in ARM64RegForFlush()
347 return INVALID_REG; in ARM64RegForFlush()
351 return INVALID_REG; in ARM64RegForFlush()
356 return INVALID_REG; in ARM64RegForFlush()
360 return INVALID_REG; in ARM64RegForFlush()
388 if (ar1 != INVALID_REG && ar2 != INVALID_REG) { in FlushAll()
459 mr[r].reg = (int)INVALID_REG; in DiscardR()
[all …]
H A DArm64CompLoadStore.cpp156 ANDI2R(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift, INVALID_REG); in Comp_ITypeMemLR()
168 ANDI2R(SCRATCH2, SCRATCH2, 0xffffff00 << shift, INVALID_REG); in Comp_ITypeMemLR()
175 ANDI2R(SCRATCH2, SCRATCH2, 0x00ffffff >> (24 - shift), INVALID_REG); in Comp_ITypeMemLR()
282 ARM64Reg targetReg = INVALID_REG; in Comp_ITypeMem()
283 ARM64Reg addrReg = INVALID_REG; in Comp_ITypeMem()
326 targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt); in Comp_ITypeMem()
327 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
349 if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) { in Comp_ITypeMem()
368 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
375 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
[all …]
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/Core/MIPS/ARM64/
H A DArm64RegCache.cpp52 mr[i].reg = INVALID_REG; in Start()
265 return INVALID_REG; in AllocateReg()
305 return INVALID_REG; in FindBestToSpill()
328 return INVALID_REG; in TryMapTempImm()
344 return INVALID_REG; in MapReg()
349 return INVALID_REG; in MapReg()
601 return INVALID_REG; in ARM64RegForFlush()
619 return INVALID_REG; in ARM64RegForFlush()
622 return INVALID_REG; in ARM64RegForFlush()
626 return INVALID_REG; in ARM64RegForFlush()
[all …]
H A DArm64RegCacheFPU.cpp61 mrInitial[i].reg = INVALID_REG; in SetupInitialRegs()
179 return INVALID_REG; in MapReg()
333 mr[r].reg = (int)INVALID_REG; in FlushR()
342 return INVALID_REG; in ARM64RegForFlush()
347 return INVALID_REG; in ARM64RegForFlush()
351 return INVALID_REG; in ARM64RegForFlush()
356 return INVALID_REG; in ARM64RegForFlush()
360 return INVALID_REG; in ARM64RegForFlush()
388 if (ar1 != INVALID_REG && ar2 != INVALID_REG) { in FlushAll()
459 mr[r].reg = (int)INVALID_REG; in DiscardR()
[all …]
H A DArm64CompLoadStore.cpp156 ANDI2R(gpr.R(rt), gpr.R(rt), 0x00ffffff >> shift, INVALID_REG); in Comp_ITypeMemLR()
168 ANDI2R(SCRATCH2, SCRATCH2, 0xffffff00 << shift, INVALID_REG); in Comp_ITypeMemLR()
175 ANDI2R(SCRATCH2, SCRATCH2, 0x00ffffff >> (24 - shift), INVALID_REG); in Comp_ITypeMemLR()
282 ARM64Reg targetReg = INVALID_REG; in Comp_ITypeMem()
283 ARM64Reg addrReg = INVALID_REG; in Comp_ITypeMem()
326 targetReg = load ? INVALID_REG : gpr.TryMapTempImm(rt); in Comp_ITypeMem()
327 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
349 if (!load && gpr.IsImm(rt) && gpr.TryMapTempImm(rt) != INVALID_REG) { in Comp_ITypeMem()
368 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
375 if (targetReg == INVALID_REG) { in Comp_ITypeMem()
[all …]
/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/Core/MIPS/ARM/
H A DArmRegCache.cpp49 mr[i].reg = INVALID_REG; in Start()
220 return INVALID_REG; in FindBestToSpill()
260 ARMReg desiredReg = INVALID_REG; in MapReg()
307 return INVALID_REG; in MapReg()
368 mreg.reg = INVALID_REG; in FlushArmReg()
373 mreg.reg = INVALID_REG; in FlushArmReg()
387 mr[mipsReg].reg = INVALID_REG; in DiscardR()
446 mr[r].reg = INVALID_REG; in FlushR()
569 mr[r].reg = INVALID_REG; in SetImm()
625 return INVALID_REG; // BAAAD in R()
[all …]
/dports/emulators/ppsspp/ppsspp-1.12.3/Core/MIPS/ARM/
H A DArmRegCache.cpp49 mr[i].reg = INVALID_REG; in Start()
220 return INVALID_REG; in FindBestToSpill()
260 ARMReg desiredReg = INVALID_REG; in MapReg()
307 return INVALID_REG; in MapReg()
368 mreg.reg = INVALID_REG; in FlushArmReg()
373 mreg.reg = INVALID_REG; in FlushArmReg()
387 mr[mipsReg].reg = INVALID_REG; in DiscardR()
446 mr[r].reg = INVALID_REG; in FlushR()
569 mr[r].reg = INVALID_REG; in SetImm()
625 return INVALID_REG; // BAAAD in R()
[all …]
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/Core/MIPS/ARM/
H A DArmRegCache.cpp49 mr[i].reg = INVALID_REG; in Start()
220 return INVALID_REG; in FindBestToSpill()
260 ARMReg desiredReg = INVALID_REG; in MapReg()
307 return INVALID_REG; in MapReg()
368 mreg.reg = INVALID_REG; in FlushArmReg()
373 mreg.reg = INVALID_REG; in FlushArmReg()
387 mr[mipsReg].reg = INVALID_REG; in DiscardR()
446 mr[r].reg = INVALID_REG; in FlushR()
569 mr[r].reg = INVALID_REG; in SetImm()
625 return INVALID_REG; // BAAAD in R()
[all …]
/dports/emulators/dolphin-emu/dolphin-3152428/Source/Core/Core/DSP/Jit/x64/
H A DDSPJitRegCache.cpp140 m_regs[i].host_reg = INVALID_REG; in DSPJitRegCache()
331 if (m_regs[i].host_reg != INVALID_REG) in FlushMemBackedRegs()
349 if (m_regs[i].host_reg != INVALID_REG) in FlushRegs()
383 if (m_regs[i].host_reg != INVALID_REG) in LoadRegs()
396 if (m_regs[i].host_reg != INVALID_REG) in SaveRegs()
411 if (m_regs[i].host_reg != INVALID_REG) in PushRegs()
547 if (tmp == INVALID_REG) in MovToHostReg()
899 return INVALID_REG; in SpillXReg()
929 return INVALID_REG; in FindFreeXReg()
935 if (reg == INVALID_REG) in FindSpillFreeXReg()
[all …]
/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/Core/MIPS/x86/
H A DRegCacheFPU.cpp270 if (vx == INVALID_REG) in TryMapRegsVS()
324 X64Reg xrs[4] = {INVALID_REG, INVALID_REG, INVALID_REG, INVALID_REG}; in LoadRegsVS()
352 if (xrs[i] == INVALID_REG) { in LoadRegsVS()
389 xrs[i] = INVALID_REG; in LoadRegsVS()
396 X64Reg res = INVALID_REG; in LoadRegsVS()
405 if (xrs[i] != INVALID_REG) { in LoadRegsVS()
450 if (xr1 == INVALID_REG) { in LoadRegsVS()
453 if (xrs[i] != INVALID_REG && xrs[i] != xr2) { in LoadRegsVS()
460 if (xr2 == INVALID_REG) { in LoadRegsVS()
463 if (xrs[i] != INVALID_REG && xrs[i] != xr1) { in LoadRegsVS()
[all …]
/dports/emulators/ppsspp/ppsspp-1.12.3/Core/MIPS/x86/
H A DRegCacheFPU.cpp270 if (vx == INVALID_REG) in TryMapRegsVS()
324 X64Reg xrs[4] = {INVALID_REG, INVALID_REG, INVALID_REG, INVALID_REG}; in LoadRegsVS()
352 if (xrs[i] == INVALID_REG) { in LoadRegsVS()
389 xrs[i] = INVALID_REG; in LoadRegsVS()
396 X64Reg res = INVALID_REG; in LoadRegsVS()
405 if (xrs[i] != INVALID_REG) { in LoadRegsVS()
450 if (xr1 == INVALID_REG) { in LoadRegsVS()
453 if (xrs[i] != INVALID_REG && xrs[i] != xr2) { in LoadRegsVS()
460 if (xr2 == INVALID_REG) { in LoadRegsVS()
463 if (xrs[i] != INVALID_REG && xrs[i] != xr1) { in LoadRegsVS()
[all …]
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/Core/MIPS/x86/
H A DRegCacheFPU.cpp270 if (vx == INVALID_REG) in TryMapRegsVS()
324 X64Reg xrs[4] = {INVALID_REG, INVALID_REG, INVALID_REG, INVALID_REG}; in LoadRegsVS()
352 if (xrs[i] == INVALID_REG) { in LoadRegsVS()
389 xrs[i] = INVALID_REG; in LoadRegsVS()
396 X64Reg res = INVALID_REG; in LoadRegsVS()
405 if (xrs[i] != INVALID_REG) { in LoadRegsVS()
450 if (xr1 == INVALID_REG) { in LoadRegsVS()
453 if (xrs[i] != INVALID_REG && xrs[i] != xr2) { in LoadRegsVS()
460 if (xr2 == INVALID_REG) { in LoadRegsVS()
463 if (xrs[i] != INVALID_REG && xrs[i] != xr1) { in LoadRegsVS()
[all …]
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/libosmesa/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-libs/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/graphics/mesa-dri/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()
/dports/lang/clover/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_assembler.c48 info->numwg = INVALID_REG; in ir3_parse_asm()
51 info->buf_addr_regs[i] = INVALID_REG; in ir3_parse_asm()

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