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Searched refs:IPR32 (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dpxa2xx_pic.c32 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
163 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
164 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
197 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dpxa2xx_pic.c35 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
165 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
166 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
201 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
202 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dpxa2xx_pic.c35 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
165 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
166 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
201 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
202 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dpxa2xx_pic.c32 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
163 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
164 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
197 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dpxa2xx_pic.c35 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
165 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
166 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
201 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
202 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dpxa2xx_pic.c32 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
163 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
164 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
197 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dpxa2xx_pic.c32 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
163 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
164 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
197 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dpxa2xx_pic.c32 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
163 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
164 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
197 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
198 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dpxa2xx_pic.c35 #define IPR32 0xb0 /* Interrupt Controller Priority register 32 */ macro
165 case IPR32 ... IPR39: in pxa2xx_pic_mem_read()
166 return s->priority[32 + ((offset - IPR32) >> 2)]; in pxa2xx_pic_mem_read()
201 case IPR32 ... IPR39: in pxa2xx_pic_mem_write()
202 s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; in pxa2xx_pic_mem_write()