/dports/lang/fpc-source/fpc-3.2.2/packages/libndsfpc/src/nds/ |
H A D | interrupts.inc | 3 IRQ_MASK = cuint; 5 IRQ_VBLANK : IRQ_MASK = (1 shl 0); (* vertical blank interrupt mask *) 8 IRQ_TIMER0 : IRQ_MASK = (1 shl 3); (* timer 0 interrupt mask *) 9 IRQ_TIMER1 : IRQ_MASK = (1 shl 4); (* timer 1 interrupt mask *) 10 IRQ_TIMER2 : IRQ_MASK = (1 shl 5); (* timer 2 interrupt mask *) 11 IRQ_TIMER3 : IRQ_MASK = (1 shl 6); (* timer 3 interrupt mask *) 12 IRQ_NETWORK : IRQ_MASK = (1 shl 7); (* serial interrupt mask *) 13 IRQ_DMA0 : IRQ_MASK = (1 shl 8); (* DMA 0 interrupt mask *) 14 IRQ_DMA1 : IRQ_MASK = (1 shl 9); (* DMA 1 interrupt mask *) 23 IRQ_CARD_LINE : IRQ_MASK = (1 shl 20); (* interrupt mask *) [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/irqchip/ |
H A D | irq-ts4800.c | 23 #define IRQ_MASK 0x4 macro 35 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_mask() 38 writew(reg | mask, data->base + IRQ_MASK); in ts4800_irq_mask() 44 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_unmask() 47 writew(reg & ~mask, data->base + IRQ_MASK); in ts4800_irq_unmask() 109 writew(0xFFFF, data->base + IRQ_MASK); in ts4800_ic_probe()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/irqchip/ |
H A D | irq-ts4800.c | 23 #define IRQ_MASK 0x4 macro 35 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_mask() 38 writew(reg | mask, data->base + IRQ_MASK); in ts4800_irq_mask() 44 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_unmask() 47 writew(reg & ~mask, data->base + IRQ_MASK); in ts4800_irq_unmask() 109 writew(0xFFFF, data->base + IRQ_MASK); in ts4800_ic_probe()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/irqchip/ |
H A D | irq-ts4800.c | 23 #define IRQ_MASK 0x4 macro 35 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_mask() 38 writew(reg | mask, data->base + IRQ_MASK); in ts4800_irq_mask() 44 u16 reg = readw(data->base + IRQ_MASK); in ts4800_irq_unmask() 47 writew(reg & ~mask, data->base + IRQ_MASK); in ts4800_irq_unmask() 109 writew(0xFFFF, data->base + IRQ_MASK); in ts4800_ic_probe()
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 59 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 66 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 73 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/ |
H A D | xilinx_irq.c | 70 u32 mask = IRQ_MASK(irq); in pic_irq_enable() 77 u32 mask = IRQ_MASK(irq); in pic_irq_disable() 84 u32 mask = IRQ_MASK(irq); in pic_irq_ack()
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/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm/ |
H A D | arm.cpp | 136 #define IRQ_MASK ((UINT32) 0x0c000000u) macro 430 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun() 471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 479 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 606 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 833 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 847 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 873 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 938 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MAS… in loadInc() 962 … *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK); in loadDec()
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/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm/ |
H A D | arm.cpp | 136 #define IRQ_MASK ((UINT32) 0x0c000000u) macro 427 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun() 463 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 598 R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 825 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 839 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 865 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 930 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv+=4))&ADDRESS_MAS… in loadInc() 954 … *deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((READ32(rbv-=4))&ADDRESS_MASK); in loadDec()
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 118 #define IRQ_MASK ((uint32_t) 0x0c000000u) macro 433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run() 465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 666 … R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 915 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 929 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 955 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1028 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv+=4))&ADDRESS… in loadInc() 1055 …*deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv-=4))&ADDRESS_MAS… in loadDec()
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm/ |
H A D | arm.cpp | 118 #define IRQ_MASK ((uint32_t) 0x0c000000u) macro 433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run() 465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state() 474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state() 666 … R15 = (cpu_read32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15 & MODE_MASK); in HandleMemSingle() 915 R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK); in HandleALU() 929 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 955 SetRegister(rdn,(rd&ADDRESS_MASK) | (rd&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK)); in HandleALU() 1028 …SetRegister( 15, (R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv+=4))&ADDRESS… in loadInc() 1055 …*deferredR15=(R15&PSR_MASK) | (R15&IRQ_MASK) | (R15&MODE_MASK) | ((cpu_read32(rbv-=4))&ADDRESS_MAS… in loadDec()
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/dports/devel/asl/asl-current/include/avr/ |
H A D | tr24.inc | 136 IRQ_MASK sfr 0x14e ; Transceiver Interrupt Enable Register 137 AWAKE_EN avrbit IRQ_MASK,7 ; Awake Interrupt Enable 138 TX_END_EN avrbit IRQ_MASK,6 ; TX_END Interrupt Enable 139 AMI_EN avrbit IRQ_MASK,5 ; Address Match Interrupt Enable 140 CCA_ED_DONE_EN avrbit IRQ_MASK,4 ; End of ED Measurement Interrupt Enable 141 RX_END_EN avrbit IRQ_MASK,3 ; RX_END Interrupt Enable 142 RX_START_EN avrbit IRQ_MASK,2 ; RX_START Interrupt Enable 143 PLL_UNLOCK_EN avrbit IRQ_MASK,1 ; PLL Unlock Interrupt Enable 144 PLL_LOCK_EN avrbit IRQ_MASK,0 ; PLL Lock Interrupt Enable
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-nomadik.c | 98 #define IRQ_MASK(mask) (mask & 0x1fffffff) macro 252 u32 mask = IRQ_MASK(0); in disable_all_interrupts() 263 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); in clear_all_interrupts() 471 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in read_i2c() 551 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in write_i2c() 707 irq = IRQ_MASK(irq); in disable_interrupts()
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-nomadik.c | 98 #define IRQ_MASK(mask) (mask & 0x1fffffff) macro 252 u32 mask = IRQ_MASK(0); in disable_all_interrupts() 263 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); in clear_all_interrupts() 471 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in read_i2c() 551 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in write_i2c() 707 irq = IRQ_MASK(irq); in disable_interrupts()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/i2c/busses/ |
H A D | i2c-nomadik.c | 98 #define IRQ_MASK(mask) (mask & 0x1fffffff) macro 252 u32 mask = IRQ_MASK(0); in disable_all_interrupts() 263 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); in clear_all_interrupts() 471 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in read_i2c() 551 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask); in write_i2c() 707 irq = IRQ_MASK(irq); in disable_interrupts()
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/dports/devel/cc65/cc65-2.19/libsrc/pce/ |
H A D | crt0.s | 67 sta IRQ_MASK ; Interrupts off 77 sta IRQ_MASK ; IRQ1 = on
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/include/asm/ |
H A D | xilinx_irq.h | 32 #define IRQ_MASK(irq) (1 << (irq & 0x1f)) macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/include/asm/ |
H A D | xilinx_irq.h | 32 #define IRQ_MASK(irq) (1 << (irq & 0x1f)) macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/include/asm/ |
H A D | xilinx_irq.h | 32 #define IRQ_MASK(irq) (1 << (irq & 0x1f)) macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/include/asm/ |
H A D | xilinx_irq.h | 32 #define IRQ_MASK(irq) (1 << (irq & 0x1f)) macro
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