IVIRT (reference) in projects: dports - OpenGrok search results

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Searched refs:IVIRT (Results 1 – 25 of 29) sorted by relevance

/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A D	micromips-opc.c	275 #define IVIRT ASE_VIRT macro 689 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 690 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 826 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 827 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1086 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1087 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1088 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1089 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1090 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	324 #define IVIRT ASE_VIRT macro 1173 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1174 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1384 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1385 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2002 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2003 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2004 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2005 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2006 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
H A D	ChangeLog-2014	`121 (IVIRT): New define. 124 IVIRT instructions.`
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A D	micromips-opc.c	277 #define IVIRT ASE_VIRT macro 702 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 703 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 841 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 842 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1109 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1110 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1111 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1112 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1113 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	332 #define IVIRT ASE_VIRT macro 1204 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1205 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1419 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1420 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2042 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2043 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2044 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2045 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2046 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
H A D	ChangeLog-2014	`121 (IVIRT): New define. 124 IVIRT instructions.`
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A D	micromips-opc.c	275 #define IVIRT ASE_VIRT macro 689 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 690 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 826 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 827 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1086 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1087 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1088 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1089 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1090 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	324 #define IVIRT ASE_VIRT macro 1173 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1174 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1384 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1385 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2002 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2003 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2004 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2005 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2006 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
H A D	ChangeLog-2014	`121 (IVIRT): New define. 124 IVIRT instructions.`
/dports/devel/gdb/gdb-11.1/opcodes/
H A D	micromips-opc.c	277 #define IVIRT ASE_VIRT macro 702 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 703 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 841 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 842 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1109 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1110 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1111 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1112 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1113 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	332 #define IVIRT ASE_VIRT macro 1204 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1205 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1419 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1420 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2042 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2043 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2044 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2045 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2046 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
H A D	ChangeLog-2014	`121 (IVIRT): New define. 124 IVIRT instructions.`
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A D	micromips-opc.c	277 #define IVIRT ASE_VIRT macro 702 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 703 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 841 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 842 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1109 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1110 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1111 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1112 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1113 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	332 #define IVIRT ASE_VIRT macro 1204 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1205 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1419 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1420 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2042 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2043 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2044 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2045 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2046 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
/dports/devel/binutils/binutils-2.37/opcodes/
H A D	micromips-opc.c	277 #define IVIRT ASE_VIRT macro 702 {"hypcall", "", 0x0000c37c, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 703 {"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 }, 841 {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 842 {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1\|RD_C0, 0, 0, IVIRT, 0 }, 1109 {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1110 {"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1111 {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1112 {"tlbgr", "", 0x0000117c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 1113 {"tlbgwi", "", 0x0000217c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	mips-opc.c	332 #define IVIRT ASE_VIRT macro 1204 {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, 1205 {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, 1419 {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 1420 {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1\|RD_C0\|LC, 0, 0, IVIRT, 0 }, 2042 {"tlbgr", "", 0x42000009, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2043 {"tlbgwi", "", 0x4200000a, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2044 {"tlbginv", "", 0x4200000b, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2045 {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, 2046 {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, [all …]
H A D	ChangeLog-2013	`937 * micromips-opc.c (IVIRT): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1024 * mips-opc.c (IVIRT): New define.`
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/kernel/
H A D	exceptions-64s.S	`128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point / macro 165 .ifndef IVIRT 166 IVIRT=1 478 .if IVIRT 891 IVIRT=0 / no virt entry point / 1052 IVIRT=0 / no virt entry point / 1069 IVIRT=0 / no virt entry point */`
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/kernel/
H A D	exceptions-64s.S	`128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point / macro 165 .ifndef IVIRT 166 IVIRT=1 478 .if IVIRT 891 IVIRT=0 / no virt entry point / 1052 IVIRT=0 / no virt entry point / 1069 IVIRT=0 / no virt entry point */`
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/kernel/
H A D	exceptions-64s.S	`128 #define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point / macro 165 .ifndef IVIRT 166 IVIRT=1 478 .if IVIRT 891 IVIRT=0 / no virt entry point / 1052 IVIRT=0 / no virt entry point / 1069 IVIRT=0 / no virt entry point */`