/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/ |
H A D | micromips-opc.c | 276 #define IVIRT64 ASE_VIRT64 macro 617 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 618 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 621 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 622 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 325 #define IVIRT64 ASE_VIRT64 macro 1068 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1069 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1074 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1075 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | micromips-opc.c | 278 #define IVIRT64 ASE_VIRT64 macro 629 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 630 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 633 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 634 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 333 #define IVIRT64 ASE_VIRT64 macro 1101 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1102 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1107 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1108 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/ |
H A D | micromips-opc.c | 276 #define IVIRT64 ASE_VIRT64 macro 617 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 618 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 621 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 622 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 325 #define IVIRT64 ASE_VIRT64 macro 1068 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1069 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1074 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1075 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|
/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | micromips-opc.c | 278 #define IVIRT64 ASE_VIRT64 macro 629 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 630 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 633 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 634 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 333 #define IVIRT64 ASE_VIRT64 macro 1101 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1102 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1107 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1108 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|
/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | micromips-opc.c | 278 #define IVIRT64 ASE_VIRT64 macro 629 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 630 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 633 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 634 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 333 #define IVIRT64 ASE_VIRT64 macro 1101 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1102 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1107 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1108 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|
/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | micromips-opc.c | 278 #define IVIRT64 ASE_VIRT64 macro 629 {"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 630 {"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, 633 {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, 634 {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
|
H A D | ChangeLog-2013 | 938 (IVIRT64): New define. 958 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, 1025 (IVIRT64): New define.
|
H A D | mips-opc.c | 333 #define IVIRT64 ASE_VIRT64 macro 1101 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1102 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 1107 {"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 }, 1108 {"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
|