/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6588 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in combineMUL_VLToVWMUL() local 6590 if ((!IsSignExt && !IsZeroExt) || !Op0.hasOneUse()) in combineMUL_VLToVWMUL() 6638 if (IsSignExt) { in combineMUL_VLToVWMUL() 6654 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in combineMUL_VLToVWMUL() 6660 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in combineMUL_VLToVWMUL()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local 6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine() 6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine() 6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local 6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine() 6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine() 6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local 6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine() 6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine() 6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local 6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine() 6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine() 6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 6324 bool IsSignExt = Op0.getOpcode() == RISCVISD::VSEXT_VL; in PerformDAGCombine() local 6326 if ((!IsSignExt && !IsZeroExt) || Op0.getOpcode() != Op1.getOpcode()) in PerformDAGCombine() 6350 unsigned ExtOpc = IsSignExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in PerformDAGCombine() 6356 unsigned WMulOpc = IsSignExt ? RISCVISD::VWMUL_VL : RISCVISD::VWMULU_VL; in PerformDAGCombine()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12739 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 12777 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 12778 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12536 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 12574 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 12575 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12744 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 12782 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 12783 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12539 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 12577 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 12578 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 12744 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 12782 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 12783 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8264 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8267 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8297 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8110 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8113 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8149 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8537 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8299 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8302 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8332 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8017 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8020 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8056 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8537 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8537 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8299 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8302 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8332 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 8504 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND; in combineShiftToMULH() local 8507 if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode()) in combineShiftToMULH() 8537 unsigned MulhOpcode = IsSignExt ? ISD::MULHS : ISD::MULHU; in combineShiftToMULH()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 13447 auto IsSignExt = [&](SDValue Op) { in PerformMVEVMULLCombine() local 13485 if (SDValue Op0 = IsSignExt(N0)) { in PerformMVEVMULLCombine() 13486 if (SDValue Op1 = IsSignExt(N1)) { in PerformMVEVMULLCombine()
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