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Searched refs:IsSourceInst (Results 1 – 16 of 16) sorted by relevance

/dports/devel/llvm90/llvm-9.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp108 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
111 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
145 bool IsSourceInst) { in validateTypes() argument
150 if (!IsSourceInst) in validateTypes()
167 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
184 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
217 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
240 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm80/llvm-8.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp108 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
111 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
145 bool IsSourceInst) { in validateTypes() argument
150 if (!IsSourceInst) in validateTypes()
167 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
184 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
217 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
240 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm70/llvm-7.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp108 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
111 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
145 bool IsSourceInst) { in validateTypes() argument
150 if (!IsSourceInst) in validateTypes()
167 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
184 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
217 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
240 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm10/llvm-10.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp116 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
119 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp116 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
119 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp117 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
120 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp116 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
119 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/devel/llvm11/llvm-11.0.1.src/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp116 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
119 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp116 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
119 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
153 bool IsSourceInst) { in validateTypes() argument
158 if (!IsSourceInst) in validateTypes()
175 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output") in validateTypes()
192 IndexedMap<OpData> &OperandMap, bool IsSourceInst) { in addDagOperandMapping() argument
225 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
248 << (IsSourceInst ? "input " : "output ") in addDagOperandMapping()