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Searched refs:LE_CSR0 (Results 1 – 25 of 27) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/amd/
H A D7990.c131 WRITERAP(lp, LE_CSR0); in load_csrs()
233 WRITERAP(lp, LE_CSR0); in init_restart_lance()
259 WRITERAP(lp, LE_CSR0); in lance_reset()
392 WRITERAP(lp, LE_CSR0); in lance_tx()
409 WRITERAP(lp, LE_CSR0); in lance_tx()
449 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */ in lance_interrupt()
490 WRITERAP(lp, LE_CSR0); in lance_interrupt()
521 WRITERAP(lp, LE_CSR0); in lance_close()
638 WRITERAP(lp, LE_CSR0); in lance_set_multicast()
662 WRITERAP(lp, LE_CSR0); in lance_poll()
H A Da2065.c142 ll->rap = LE_CSR0; in load_csrs()
223 ll->rap = LE_CSR0; in init_restart_lance()
357 ll->rap = LE_CSR0; in lance_tx()
374 ll->rap = LE_CSR0; in lance_tx()
417 ll->rap = LE_CSR0; /* LANCE Controller Status */ in lance_interrupt()
453 ll->rap = LE_CSR0; in lance_interrupt()
466 ll->rap = LE_CSR0; in lance_open()
492 ll->rap = LE_CSR0; in lance_close()
506 ll->rap = LE_CSR0; in lance_reset()
622 ll->rap = LE_CSR0; in lance_set_multicast()
H A Ddeclance.c93 #define LE_CSR0 0 macro
321 writereg(&ll->rap, LE_CSR0); in load_csrs()
532 writereg(&ll->rap, LE_CSR0); in init_restart_lance()
675 writereg(&ll->rap, LE_CSR0); in lance_tx()
691 writereg(&ll->rap, LE_CSR0); in lance_tx()
741 writereg(&ll->rap, LE_CSR0); in lance_interrupt()
788 writereg(&ll->rap, LE_CSR0); in lance_open()
848 writereg(&ll->rap, LE_CSR0); in lance_close()
877 writereg(&ll->rap, LE_CSR0); in lance_reset()
989 writereg(&ll->rap, LE_CSR0); in lance_set_multicast()
H A Da2065.h50 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A D7990.h133 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A Dsunlance.c121 #define LE_CSR0 0 macro
278 sbus_writew(LE_CSR0, __base + RAP); \
312 sbus_writew(LE_CSR0, lp->lregs + RAP); in load_csrs()
470 sbus_writew(LE_CSR0, lp->lregs + RAP); in init_restart_lance()
816 sbus_writew(LE_CSR0, lp->lregs + RAP); in lance_interrupt()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/amd/
H A D7990.c131 WRITERAP(lp, LE_CSR0); in load_csrs()
233 WRITERAP(lp, LE_CSR0); in init_restart_lance()
259 WRITERAP(lp, LE_CSR0); in lance_reset()
392 WRITERAP(lp, LE_CSR0); in lance_tx()
409 WRITERAP(lp, LE_CSR0); in lance_tx()
449 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */ in lance_interrupt()
490 WRITERAP(lp, LE_CSR0); in lance_interrupt()
521 WRITERAP(lp, LE_CSR0); in lance_close()
638 WRITERAP(lp, LE_CSR0); in lance_set_multicast()
662 WRITERAP(lp, LE_CSR0); in lance_poll()
H A Da2065.c142 ll->rap = LE_CSR0; in load_csrs()
223 ll->rap = LE_CSR0; in init_restart_lance()
357 ll->rap = LE_CSR0; in lance_tx()
374 ll->rap = LE_CSR0; in lance_tx()
417 ll->rap = LE_CSR0; /* LANCE Controller Status */ in lance_interrupt()
453 ll->rap = LE_CSR0; in lance_interrupt()
466 ll->rap = LE_CSR0; in lance_open()
492 ll->rap = LE_CSR0; in lance_close()
506 ll->rap = LE_CSR0; in lance_reset()
622 ll->rap = LE_CSR0; in lance_set_multicast()
H A Ddeclance.c93 #define LE_CSR0 0 macro
321 writereg(&ll->rap, LE_CSR0); in load_csrs()
532 writereg(&ll->rap, LE_CSR0); in init_restart_lance()
675 writereg(&ll->rap, LE_CSR0); in lance_tx()
691 writereg(&ll->rap, LE_CSR0); in lance_tx()
741 writereg(&ll->rap, LE_CSR0); in lance_interrupt()
788 writereg(&ll->rap, LE_CSR0); in lance_open()
848 writereg(&ll->rap, LE_CSR0); in lance_close()
877 writereg(&ll->rap, LE_CSR0); in lance_reset()
989 writereg(&ll->rap, LE_CSR0); in lance_set_multicast()
H A Da2065.h50 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A D7990.h133 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A Dsunlance.c121 #define LE_CSR0 0 macro
278 sbus_writew(LE_CSR0, __base + RAP); \
312 sbus_writew(LE_CSR0, lp->lregs + RAP); in load_csrs()
470 sbus_writew(LE_CSR0, lp->lregs + RAP); in init_restart_lance()
816 sbus_writew(LE_CSR0, lp->lregs + RAP); in lance_interrupt()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/amd/
H A D7990.c131 WRITERAP(lp, LE_CSR0); in load_csrs()
233 WRITERAP(lp, LE_CSR0); in init_restart_lance()
259 WRITERAP(lp, LE_CSR0); in lance_reset()
392 WRITERAP(lp, LE_CSR0); in lance_tx()
409 WRITERAP(lp, LE_CSR0); in lance_tx()
449 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */ in lance_interrupt()
490 WRITERAP(lp, LE_CSR0); in lance_interrupt()
521 WRITERAP(lp, LE_CSR0); in lance_close()
638 WRITERAP(lp, LE_CSR0); in lance_set_multicast()
662 WRITERAP(lp, LE_CSR0); in lance_poll()
H A Da2065.c142 ll->rap = LE_CSR0; in load_csrs()
223 ll->rap = LE_CSR0; in init_restart_lance()
357 ll->rap = LE_CSR0; in lance_tx()
374 ll->rap = LE_CSR0; in lance_tx()
417 ll->rap = LE_CSR0; /* LANCE Controller Status */ in lance_interrupt()
453 ll->rap = LE_CSR0; in lance_interrupt()
466 ll->rap = LE_CSR0; in lance_open()
492 ll->rap = LE_CSR0; in lance_close()
506 ll->rap = LE_CSR0; in lance_reset()
622 ll->rap = LE_CSR0; in lance_set_multicast()
H A Ddeclance.c93 #define LE_CSR0 0 macro
321 writereg(&ll->rap, LE_CSR0); in load_csrs()
532 writereg(&ll->rap, LE_CSR0); in init_restart_lance()
675 writereg(&ll->rap, LE_CSR0); in lance_tx()
691 writereg(&ll->rap, LE_CSR0); in lance_tx()
741 writereg(&ll->rap, LE_CSR0); in lance_interrupt()
788 writereg(&ll->rap, LE_CSR0); in lance_open()
848 writereg(&ll->rap, LE_CSR0); in lance_close()
877 writereg(&ll->rap, LE_CSR0); in lance_reset()
989 writereg(&ll->rap, LE_CSR0); in lance_set_multicast()
H A Da2065.h50 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A D7990.h133 #define LE_CSR0 0x0000 /* LANCE Controller Status */ macro
H A Dsunlance.c121 #define LE_CSR0 0 macro
278 sbus_writew(LE_CSR0, __base + RAP); \
312 sbus_writew(LE_CSR0, lp->lregs + RAP); in load_csrs()
470 sbus_writew(LE_CSR0, lp->lregs + RAP); in init_restart_lance()
816 sbus_writew(LE_CSR0, lp->lregs + RAP); in lance_interrupt()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/
H A Dam7990.c374 isr = (*sc->sc_rdcsr)(sc, LE_CSR0) | sc->sc_saved_csr0; in am7990_intr()
390 (*sc->sc_wrcsr)(sc, LE_CSR0, isr); in am7990_intr()
391 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA); in am7990_intr()
393 (*sc->sc_wrcsr)(sc, LE_CSR0, in am7990_intr()
522 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); in am7990_start()
550 (*sc->sc_rdcsr)(sc, LE_CSR0)); in am7990_recv_print()
575 (*sc->sc_rdcsr)(sc, LE_CSR0)); in am7990_xmit_print()
H A Dlance.c276 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP); in lance_stop()
290 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_STOP); in lance_init()
310 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INIT); in lance_init()
314 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON) in lance_init()
317 if ((*sc->sc_rdcsr)(sc, LE_CSR0) & LE_C0_IDON) { in lance_init()
319 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT); in lance_init()
H A Dam79900.c405 isr = (*sc->sc_rdcsr)(sc, LE_CSR0) | sc->sc_saved_csr0; in am79900_intr()
415 (*sc->sc_wrcsr)(sc, LE_CSR0, in am79900_intr()
543 (*sc->sc_wrcsr)(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); in am79900_start()
571 (*sc->sc_rdcsr)(sc, LE_CSR0)); in am79900_recv_print()
595 (*sc->sc_rdcsr)(sc, LE_CSR0)); in am79900_xmit_print()
H A Dlancereg.h134 #define LE_CSR0 0x0000 /* Control and status register */ macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/isa/
H A Ddepca_isa.c160 bus_space_write_2(iot, ioh, DEPCA_RAP, LE_CSR0); in depca_isa_probe()
164 bus_space_write_2(iot, ioh, DEPCA_RAP, LE_CSR0); in depca_isa_probe()
H A Dif_le_isa.c228 bus_space_write_2(iot, ioh, rap, LE_CSR0); in lance_isa_probe()
232 bus_space_write_2(iot, ioh, rap, LE_CSR0); in lance_isa_probe()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dif_pcn.c1112 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); in pcn_start()
1230 csr0 = pcn_csr_read(sc, LE_CSR0); in pcn_intr()
1237 pcn_csr_write(sc, LE_CSR0, csr0 & in pcn_intr()
1797 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); in pcn_init()
1800 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) in pcn_init()
1817 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); in pcn_init()
1876 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); in pcn_stop()

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