1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_PWR_H
22 #define STM32G4xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47
48 /* Exported types ------------------------------------------------------------*/
49 /* Exported constants --------------------------------------------------------*/
50 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
51 * @{
52 */
53
54 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
55 * @brief Flags defines which can be used with LL_PWR_WriteReg function
56 * @{
57 */
58 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
59 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
60 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
61 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
62 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
63 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
64 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
74 #define LL_PWR_SR1_SBF PWR_SR1_SBF
75 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
76 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
77 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
78 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
79 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
80 #if defined(PWR_SR2_PVMO4)
81 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
82 #endif /* PWR_SR2_PVMO4 */
83 #if defined(PWR_SR2_PVMO3)
84 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
85 #endif /* PWR_SR2_PVMO3 */
86 #if defined(PWR_SR2_PVMO2)
87 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
88 #endif /* PWR_SR2_PVMO2 */
89 #if defined(PWR_SR2_PVMO1)
90 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
91 #endif /* PWR_SR2_PVMO1 */
92 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
93 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
94 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
95 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
96 /**
97 * @}
98 */
99
100 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
101 * @{
102 */
103 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
104 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
105 /**
106 * @}
107 */
108
109 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
110 * @{
111 */
112 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
113 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
114 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
115 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
116 /**
117 * @}
118 */
119
120 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
121 * @{
122 */
123 #if defined(PWR_CR2_PVME1)
124 #define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
125 #endif
126 #if defined(PWR_CR2_PVME2)
127 #define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
128 #endif
129 #if defined(PWR_CR2_PVME3)
130 #define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
131 #endif
132 #if defined(PWR_CR2_PVME4)
133 #define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
134 #endif
135 /**
136 * @}
137 */
138
139 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
140 * @{
141 */
142 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
143 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
144 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
145 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
146 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
147 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
148 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
149 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
150 /**
151 * @}
152 */
153
154 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
155 * @{
156 */
157 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
158 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
159 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
160 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
161 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
162 /**
163 * @}
164 */
165
166 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
167 * @{
168 */
169 #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
170 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
171 /**
172 * @}
173 */
174
175 /** @defgroup PWR_LL_EC_GPIO GPIO
176 * @{
177 */
178 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
179 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
180 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
181 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
182 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
183 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
184 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
185 /**
186 * @}
187 */
188
189 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
190 * @{
191 */
192 #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
193 #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
194 #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
195 #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
196 #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
197 #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
198 #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
199 #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
200 #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
201 #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
202 #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
203 #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
204 #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
205 #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
206 #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
207 #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
208 /**
209 * @}
210 */
211
212 /**
213 * @}
214 */
215
216 /* Exported macro ------------------------------------------------------------*/
217 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
218 * @{
219 */
220
221 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
222 * @{
223 */
224
225 /**
226 * @brief Write a value in PWR register
227 * @param __REG__ Register to be written
228 * @param __VALUE__ Value to be written in the register
229 * @retval None
230 */
231 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
232
233 /**
234 * @brief Read a value in PWR register
235 * @param __REG__ Register to be read
236 * @retval Register value
237 */
238 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
239 /**
240 * @}
241 */
242
243 /**
244 * @}
245 */
246
247
248 /* Exported functions --------------------------------------------------------*/
249 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
250 * @{
251 */
252
253 /** @defgroup PWR_LL_EF_Configuration Configuration
254 * @{
255 */
256
257 /**
258 * @brief Switch the regulator from main mode to low-power mode
259 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
260 * @retval None
261 */
LL_PWR_EnableLowPowerRunMode(void)262 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
263 {
264 SET_BIT(PWR->CR1, PWR_CR1_LPR);
265 }
266
267 /**
268 * @brief Switch the regulator from low-power mode to main mode
269 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
270 * @retval None
271 */
LL_PWR_DisableLowPowerRunMode(void)272 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
273 {
274 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
275 }
276
277 /**
278 * @brief Check if the regulator is in low-power mode
279 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
280 * @retval State of bit (1 or 0).
281 */
LL_PWR_IsEnabledLowPowerRunMode(void)282 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
283 {
284 uint32_t temp;
285 temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
286
287 return ((temp == (PWR_CR1_LPR))?1U:0U);
288
289 }
290
291 /**
292 * @brief Switch from run main mode to run low-power mode.
293 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
294 * @retval None
295 */
LL_PWR_EnterLowPowerRunMode(void)296 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
297 {
298 LL_PWR_EnableLowPowerRunMode();
299 }
300
301 /**
302 * @brief Switch from run main mode to low-power mode.
303 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
304 * @retval None
305 */
LL_PWR_ExitLowPowerRunMode(void)306 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
307 {
308 LL_PWR_DisableLowPowerRunMode();
309 }
310
311 /**
312 * @brief Set the main internal regulator output voltage
313 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
314 * @param VoltageScaling This parameter can be one of the following values:
315 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
316 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
317 * @retval None
318 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)319 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
320 {
321 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
322 }
323
324 /**
325 * @brief Get the main internal regulator output voltage
326 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
327 * @retval Returned value can be one of the following values:
328 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
329 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
330 */
LL_PWR_GetRegulVoltageScaling(void)331 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
332 {
333 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
334 }
335
336 #if defined(PWR_CR5_R1MODE)
337 /**
338 * @brief Enable main regulator voltage range 1 boost mode
339 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
340 * @retval None
341 */
LL_PWR_EnableRange1BoostMode(void)342 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
343 {
344 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
345 }
346
347 /**
348 * @brief Disable main regulator voltage range 1 boost mode
349 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
350 * @retval None
351 */
LL_PWR_DisableRange1BoostMode(void)352 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
353 {
354 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
355 }
356
357 /**
358 * @brief Check if the main regulator voltage range 1 boost mode is enabled
359 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
360 * @retval Inverted state of bit (0 or 1).
361 */
LL_PWR_IsEnabledRange1BoostMode(void)362 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
363 {
364 uint32_t temp;
365 temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
366
367 return ((temp == (0U))?1U:0U);
368 }
369 #endif /* PWR_CR5_R1MODE */
370
371 /**
372 * @brief Enable access to the backup domain
373 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
374 * @retval None
375 */
LL_PWR_EnableBkUpAccess(void)376 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
377 {
378 SET_BIT(PWR->CR1, PWR_CR1_DBP);
379 }
380
381 /**
382 * @brief Disable access to the backup domain
383 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
384 * @retval None
385 */
LL_PWR_DisableBkUpAccess(void)386 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
387 {
388 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
389 }
390
391 /**
392 * @brief Check if the backup domain is enabled
393 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
394 * @retval State of bit (1 or 0).
395 */
LL_PWR_IsEnabledBkUpAccess(void)396 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
397 {
398 uint32_t temp;
399 temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
400
401 return ((temp == (PWR_CR1_DBP))?1U:0U);
402
403 }
404
405 /**
406 * @brief Set Low-Power mode
407 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
408 * @param LowPowerMode This parameter can be one of the following values:
409 * @arg @ref LL_PWR_MODE_STOP0
410 * @arg @ref LL_PWR_MODE_STOP1
411 * @arg @ref LL_PWR_MODE_STANDBY
412 * @arg @ref LL_PWR_MODE_SHUTDOWN
413 * @retval None
414 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)415 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
416 {
417 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
418 }
419
420 /**
421 * @brief Get Low-Power mode
422 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
423 * @retval Returned value can be one of the following values:
424 * @arg @ref LL_PWR_MODE_STOP0
425 * @arg @ref LL_PWR_MODE_STOP1
426 * @arg @ref LL_PWR_MODE_STANDBY
427 * @arg @ref LL_PWR_MODE_SHUTDOWN
428 */
LL_PWR_GetPowerMode(void)429 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
430 {
431 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
432 }
433
434 #if defined(PWR_CR3_UCPD_STDBY)
435 /**
436 * @brief Enable (write 1) the USB Type-C and Power Delivery standby mode.
437 * @note Enable just before entering standby when using UCPD1.
438 * @rmtoll CR3 UCPD1_STDBY LL_PWR_EnableUSBStandByModePD
439 * @retval None
440 */
LL_PWR_EnableUSBStandByModePD(void)441 __STATIC_INLINE void LL_PWR_EnableUSBStandByModePD(void)
442 {
443 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
444 }
445
446 /**
447 * @brief Disable (write 0) USB Type-C and Power Delivery standby mode.
448 * @note Disable immediately after standby exit when using UCPD1,
449 * (and before writing any UCPD1 registers).
450 * @rmtoll CR3 UCPD1_STDBY LL_PWR_DisableUSBStandByModePD
451 * @retval None
452 */
LL_PWR_DisableUSBStandByModePD(void)453 __STATIC_INLINE void LL_PWR_DisableUSBStandByModePD(void)
454 {
455 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
456 }
457
458 /**
459 * @brief Check the USB Type-C and Power Delivery standby mode.
460 * @rmtoll CR3 UCPD1_STDBY LL_PWR_IsEnabledUSBStandByModePD
461 * @retval State of bit (1 or 0).
462 */
LL_PWR_IsEnabledUSBStandByModePD(void)463 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBStandByModePD(void)
464 {
465
466 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))?1UL:0UL);
467
468 }
469 #endif /* PWR_CR3_UCPD_STDBY */
470
471 #if defined(PWR_CR3_UCPD_DBDIS)
472 /**
473 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
474 * on UCPD CC1 and CC2 pins.
475 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
476 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
477 * to disable it in all cases, either to stop this pull-down or to hand over
478 * control to the UCPD (which should therefore be initialized before doing the disable).
479 * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
480 * @retval None
481 */
LL_PWR_EnableUCPDDeadBattery(void)482 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
483 {
484 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
485 }
486
487 /**
488 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
489 * on UCPD CC1 and CC2 pins.
490 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
491 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
492 * to disable it in all cases, either to stop this pull-down or to hand over
493 * control to the UCPD (which should therefore be initialized before doing the disable).
494 * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
495 * @retval None
496 */
LL_PWR_DisableUCPDDeadBattery(void)497 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
498 {
499 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
500 }
501
502 /**
503 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
504 * on UCPD CC1 and CC2 pins.
505 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
506 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
507 * to disable it in all cases, either to stop this pull-down or to hand over
508 * control to the UCPD (which should therefore be initialized before doing the disable).
509 * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
510 * @retval State of feature (1 : enabled; 0 : disabled).
511 */
LL_PWR_IsEnabledUCPDDeadBattery(void)512 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
513 {
514 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
515 }
516 #endif /* PWR_CR3_UCPD_DBDIS */
517
518 #if defined(PWR_CR2_USV)
519 /**
520 * @brief Enable VDDUSB supply
521 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
522 * @retval None
523 */
LL_PWR_EnableVddUSB(void)524 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
525 {
526 SET_BIT(PWR->CR2, PWR_CR2_USV);
527 }
528
529 /**
530 * @brief Disable VDDUSB supply
531 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
532 * @retval None
533 */
LL_PWR_DisableVddUSB(void)534 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
535 {
536 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
537 }
538
539 /**
540 * @brief Check if VDDUSB supply is enabled
541 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
542 * @retval State of bit (1 or 0).
543 */
LL_PWR_IsEnabledVddUSB(void)544 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
545 {
546 uint32_t temp;
547 temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
548
549 return ((temp == (PWR_CR2_USV))?1U:0U);
550
551 }
552 #endif
553
554 #if defined(PWR_CR2_IOSV)
555 /**
556 * @brief Enable VDDIO2 supply
557 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
558 * @retval None
559 */
LL_PWR_EnableVddIO2(void)560 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
561 {
562 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
563 }
564
565 /**
566 * @brief Disable VDDIO2 supply
567 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
568 * @retval None
569 */
LL_PWR_DisableVddIO2(void)570 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
571 {
572 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
573 }
574
575 /**
576 * @brief Check if VDDIO2 supply is enabled
577 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
578 * @retval State of bit (1 or 0).
579 */
LL_PWR_IsEnabledVddIO2(void)580 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
581 {
582 uint32_t temp;
583 temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
584
585 return ((temp == (PWR_CR2_IOSV))?1U:0U);
586
587 }
588 #endif
589
590 /**
591 * @brief Enable the Power Voltage Monitoring on a peripheral
592 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
593 * CR2 PVME2 LL_PWR_EnablePVM\n
594 * CR2 PVME3 LL_PWR_EnablePVM\n
595 * CR2 PVME4 LL_PWR_EnablePVM
596 * @param PeriphVoltage This parameter can be one of the following values:
597 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
598 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
599 * @arg @ref LL_PWR_PVM_VDDA_ADC
600 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
601 *
602 * (*) value not defined in all devices
603 * @retval None
604 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)605 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
606 {
607 SET_BIT(PWR->CR2, PeriphVoltage);
608 }
609
610 /**
611 * @brief Disable the Power Voltage Monitoring on a peripheral
612 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
613 * CR2 PVME2 LL_PWR_DisablePVM\n
614 * CR2 PVME3 LL_PWR_DisablePVM\n
615 * CR2 PVME4 LL_PWR_DisablePVM
616 * @param PeriphVoltage This parameter can be one of the following values:
617 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
618 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
619 * @arg @ref LL_PWR_PVM_VDDA_ADC
620 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
621 *
622 * (*) value not defined in all devices
623 * @retval None
624 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)625 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
626 {
627 CLEAR_BIT(PWR->CR2, PeriphVoltage);
628 }
629
630 /**
631 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
632 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
633 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
634 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
635 * CR2 PVME4 LL_PWR_IsEnabledPVM
636 * @param PeriphVoltage This parameter can be one of the following values:
637 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
638 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
639 * @arg @ref LL_PWR_PVM_VDDA_ADC
640 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
641 *
642 * (*) value not defined in all devices
643 * @retval State of bit (1 or 0).
644 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)645 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
646 {
647 uint32_t temp;
648 temp = READ_BIT(PWR->CR2, PeriphVoltage);
649
650 return ((temp == (PeriphVoltage))?1U:0U);
651
652 }
653
654 /**
655 * @brief Configure the voltage threshold detected by the Power Voltage Detector
656 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
657 * @param PVDLevel This parameter can be one of the following values:
658 * @arg @ref LL_PWR_PVDLEVEL_0
659 * @arg @ref LL_PWR_PVDLEVEL_1
660 * @arg @ref LL_PWR_PVDLEVEL_2
661 * @arg @ref LL_PWR_PVDLEVEL_3
662 * @arg @ref LL_PWR_PVDLEVEL_4
663 * @arg @ref LL_PWR_PVDLEVEL_5
664 * @arg @ref LL_PWR_PVDLEVEL_6
665 * @arg @ref LL_PWR_PVDLEVEL_7
666 * @retval None
667 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)668 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
669 {
670 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
671 }
672
673 /**
674 * @brief Get the voltage threshold detection
675 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
676 * @retval Returned value can be one of the following values:
677 * @arg @ref LL_PWR_PVDLEVEL_0
678 * @arg @ref LL_PWR_PVDLEVEL_1
679 * @arg @ref LL_PWR_PVDLEVEL_2
680 * @arg @ref LL_PWR_PVDLEVEL_3
681 * @arg @ref LL_PWR_PVDLEVEL_4
682 * @arg @ref LL_PWR_PVDLEVEL_5
683 * @arg @ref LL_PWR_PVDLEVEL_6
684 * @arg @ref LL_PWR_PVDLEVEL_7
685 */
LL_PWR_GetPVDLevel(void)686 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
687 {
688 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
689 }
690
691 /**
692 * @brief Enable Power Voltage Detector
693 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
694 * @retval None
695 */
LL_PWR_EnablePVD(void)696 __STATIC_INLINE void LL_PWR_EnablePVD(void)
697 {
698 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
699 }
700
701 /**
702 * @brief Disable Power Voltage Detector
703 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
704 * @retval None
705 */
LL_PWR_DisablePVD(void)706 __STATIC_INLINE void LL_PWR_DisablePVD(void)
707 {
708 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
709 }
710
711 /**
712 * @brief Check if Power Voltage Detector is enabled
713 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
714 * @retval State of bit (1 or 0).
715 */
LL_PWR_IsEnabledPVD(void)716 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
717 {
718 uint32_t temp;
719 temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
720
721 return ((temp == (PWR_CR2_PVDE))?1U:0U);
722 }
723
724 /**
725 * @brief Enable Internal Wake-up line
726 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
727 * @retval None
728 */
LL_PWR_EnableInternWU(void)729 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
730 {
731 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
732 }
733
734 /**
735 * @brief Disable Internal Wake-up line
736 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
737 * @retval None
738 */
LL_PWR_DisableInternWU(void)739 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
740 {
741 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
742 }
743
744 /**
745 * @brief Check if Internal Wake-up line is enabled
746 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
747 * @retval State of bit (1 or 0).
748 */
LL_PWR_IsEnabledInternWU(void)749 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
750 {
751 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
752 }
753
754 #if defined(PWR_CR3_UCPD_STDBY)
755 /**
756 * @brief Enable USB Type-C and Power Delivery standby mode.
757 * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableStandByModePD
758 * @retval None
759 */
LL_PWR_EnableStandByModePD(void)760 __STATIC_INLINE void LL_PWR_EnableStandByModePD(void)
761 {
762 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
763 }
764
765 /**
766 * @brief Disable USB Type-C and Power Delivery standby mode.
767 * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableStandByModePD
768 * @retval None
769 */
LL_PWR_DisableStandByModePD(void)770 __STATIC_INLINE void LL_PWR_DisableStandByModePD(void)
771 {
772 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
773 }
774 #endif /* PWR_CR3_UCPD_STDBY */
775
776 /**
777 * @brief Enable pull-up and pull-down configuration
778 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
779 * @retval None
780 */
LL_PWR_EnablePUPDCfg(void)781 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
782 {
783 SET_BIT(PWR->CR3, PWR_CR3_APC);
784 }
785
786 /**
787 * @brief Disable pull-up and pull-down configuration
788 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
789 * @retval None
790 */
LL_PWR_DisablePUPDCfg(void)791 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
792 {
793 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
794 }
795
796 /**
797 * @brief Check if pull-up and pull-down configuration is enabled
798 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
799 * @retval State of bit (1 or 0).
800 */
LL_PWR_IsEnabledPUPDCfg(void)801 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
802 {
803 uint32_t temp;
804 temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
805
806 return ((temp == (PWR_CR3_APC))?1U:0U);
807 }
808
809 /**
810 * @brief Enable SRAM2 content retention in Standby mode
811 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
812 * @retval None
813 */
LL_PWR_EnableSRAM2Retention(void)814 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
815 {
816 SET_BIT(PWR->CR3, PWR_CR3_RRS);
817 }
818
819 /**
820 * @brief Disable SRAM2 content retention in Standby mode
821 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
822 * @retval None
823 */
LL_PWR_DisableSRAM2Retention(void)824 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
825 {
826 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
827 }
828
829 /**
830 * @brief Check if SRAM2 content retention in Standby mode is enabled
831 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
832 * @retval State of bit (1 or 0).
833 */
LL_PWR_IsEnabledSRAM2Retention(void)834 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
835 {
836 uint32_t temp;
837 temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
838
839 return ((temp == (PWR_CR3_RRS))?1U:0U);
840 }
841
842 /**
843 * @brief Enable the WakeUp PINx functionality
844 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
845 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
846 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
847 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
848 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
849 * @param WakeUpPin This parameter can be one of the following values:
850 * @arg @ref LL_PWR_WAKEUP_PIN1
851 * @arg @ref LL_PWR_WAKEUP_PIN2
852 * @arg @ref LL_PWR_WAKEUP_PIN3
853 * @arg @ref LL_PWR_WAKEUP_PIN4
854 * @arg @ref LL_PWR_WAKEUP_PIN5
855 * @retval None
856 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)857 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
858 {
859 SET_BIT(PWR->CR3, WakeUpPin);
860 }
861
862 /**
863 * @brief Disable the WakeUp PINx functionality
864 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
865 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
866 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
867 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
868 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
869 * @param WakeUpPin This parameter can be one of the following values:
870 * @arg @ref LL_PWR_WAKEUP_PIN1
871 * @arg @ref LL_PWR_WAKEUP_PIN2
872 * @arg @ref LL_PWR_WAKEUP_PIN3
873 * @arg @ref LL_PWR_WAKEUP_PIN4
874 * @arg @ref LL_PWR_WAKEUP_PIN5
875 * @retval None
876 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)877 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
878 {
879 CLEAR_BIT(PWR->CR3, WakeUpPin);
880 }
881
882 /**
883 * @brief Check if the WakeUp PINx functionality is enabled
884 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
885 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
886 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
887 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
888 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
889 * @param WakeUpPin This parameter can be one of the following values:
890 * @arg @ref LL_PWR_WAKEUP_PIN1
891 * @arg @ref LL_PWR_WAKEUP_PIN2
892 * @arg @ref LL_PWR_WAKEUP_PIN3
893 * @arg @ref LL_PWR_WAKEUP_PIN4
894 * @arg @ref LL_PWR_WAKEUP_PIN5
895 * @retval State of bit (1 or 0).
896 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)897 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
898 {
899 uint32_t temp;
900 temp = READ_BIT(PWR->CR3, WakeUpPin);
901
902 return ((temp == (WakeUpPin))?1U:0U);
903 }
904
905 /**
906 * @brief Set the resistor impedance
907 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
908 * @param Resistor This parameter can be one of the following values:
909 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
910 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
911 * @retval None
912 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)913 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
914 {
915 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
916 }
917
918 /**
919 * @brief Get the resistor impedance
920 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
923 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
924 */
LL_PWR_GetBattChargResistor(void)925 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
926 {
927 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
928 }
929
930 /**
931 * @brief Enable battery charging
932 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
933 * @retval None
934 */
LL_PWR_EnableBatteryCharging(void)935 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
936 {
937 SET_BIT(PWR->CR4, PWR_CR4_VBE);
938 }
939
940 /**
941 * @brief Disable battery charging
942 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
943 * @retval None
944 */
LL_PWR_DisableBatteryCharging(void)945 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
946 {
947 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
948 }
949
950 /**
951 * @brief Check if battery charging is enabled
952 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
953 * @retval State of bit (1 or 0).
954 */
LL_PWR_IsEnabledBatteryCharging(void)955 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
956 {
957 uint32_t temp;
958 temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
959
960 return ((temp == (PWR_CR4_VBE))?1U:0U);
961 }
962
963 /**
964 * @brief Set the Wake-Up pin polarity low for the event detection
965 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
966 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
967 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
968 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
969 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
970 * @param WakeUpPin This parameter can be one of the following values:
971 * @arg @ref LL_PWR_WAKEUP_PIN1
972 * @arg @ref LL_PWR_WAKEUP_PIN2
973 * @arg @ref LL_PWR_WAKEUP_PIN3
974 * @arg @ref LL_PWR_WAKEUP_PIN4
975 * @arg @ref LL_PWR_WAKEUP_PIN5
976 * @retval None
977 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)978 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
979 {
980 SET_BIT(PWR->CR4, WakeUpPin);
981 }
982
983 /**
984 * @brief Set the Wake-Up pin polarity high for the event detection
985 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
986 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
987 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
988 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
989 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
990 * @param WakeUpPin This parameter can be one of the following values:
991 * @arg @ref LL_PWR_WAKEUP_PIN1
992 * @arg @ref LL_PWR_WAKEUP_PIN2
993 * @arg @ref LL_PWR_WAKEUP_PIN3
994 * @arg @ref LL_PWR_WAKEUP_PIN4
995 * @arg @ref LL_PWR_WAKEUP_PIN5
996 * @retval None
997 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)998 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
999 {
1000 CLEAR_BIT(PWR->CR4, WakeUpPin);
1001 }
1002
1003 /**
1004 * @brief Get the Wake-Up pin polarity for the event detection
1005 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1006 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1007 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1008 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1009 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1010 * @param WakeUpPin This parameter can be one of the following values:
1011 * @arg @ref LL_PWR_WAKEUP_PIN1
1012 * @arg @ref LL_PWR_WAKEUP_PIN2
1013 * @arg @ref LL_PWR_WAKEUP_PIN3
1014 * @arg @ref LL_PWR_WAKEUP_PIN4
1015 * @arg @ref LL_PWR_WAKEUP_PIN5
1016 * @retval State of bit (1 or 0).
1017 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1018 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1019 {
1020 uint32_t temp;
1021 temp = READ_BIT(PWR->CR4, WakeUpPin);
1022
1023 return ((temp == (WakeUpPin))?1U:0U);
1024 }
1025
1026 /**
1027 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1028 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1029 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1030 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1031 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1032 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1033 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1034 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1035 * @param GPIO This parameter can be one of the following values:
1036 * @arg @ref LL_PWR_GPIO_A
1037 * @arg @ref LL_PWR_GPIO_B
1038 * @arg @ref LL_PWR_GPIO_C
1039 * @arg @ref LL_PWR_GPIO_D
1040 * @arg @ref LL_PWR_GPIO_E
1041 * @arg @ref LL_PWR_GPIO_F
1042 * @arg @ref LL_PWR_GPIO_G
1043 *
1044 * (*) value not defined in all devices
1045 * @param GPIONumber This parameter can be one of the following values:
1046 * @arg @ref LL_PWR_GPIO_BIT_0
1047 * @arg @ref LL_PWR_GPIO_BIT_1
1048 * @arg @ref LL_PWR_GPIO_BIT_2
1049 * @arg @ref LL_PWR_GPIO_BIT_3
1050 * @arg @ref LL_PWR_GPIO_BIT_4
1051 * @arg @ref LL_PWR_GPIO_BIT_5
1052 * @arg @ref LL_PWR_GPIO_BIT_6
1053 * @arg @ref LL_PWR_GPIO_BIT_7
1054 * @arg @ref LL_PWR_GPIO_BIT_8
1055 * @arg @ref LL_PWR_GPIO_BIT_9
1056 * @arg @ref LL_PWR_GPIO_BIT_10
1057 * @arg @ref LL_PWR_GPIO_BIT_11
1058 * @arg @ref LL_PWR_GPIO_BIT_12
1059 * @arg @ref LL_PWR_GPIO_BIT_13
1060 * @arg @ref LL_PWR_GPIO_BIT_14
1061 * @arg @ref LL_PWR_GPIO_BIT_15
1062 * @retval None
1063 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1064 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1065 {
1066 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1067 }
1068
1069 /**
1070 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1071 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1072 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1073 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1074 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1075 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1076 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1077 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1078 * @param GPIO This parameter can be one of the following values:
1079 * @arg @ref LL_PWR_GPIO_A
1080 * @arg @ref LL_PWR_GPIO_B
1081 * @arg @ref LL_PWR_GPIO_C
1082 * @arg @ref LL_PWR_GPIO_D
1083 * @arg @ref LL_PWR_GPIO_E
1084 * @arg @ref LL_PWR_GPIO_F
1085 * @arg @ref LL_PWR_GPIO_G
1086 *
1087 * (*) value not defined in all devices
1088 * @param GPIONumber This parameter can be one of the following values:
1089 * @arg @ref LL_PWR_GPIO_BIT_0
1090 * @arg @ref LL_PWR_GPIO_BIT_1
1091 * @arg @ref LL_PWR_GPIO_BIT_2
1092 * @arg @ref LL_PWR_GPIO_BIT_3
1093 * @arg @ref LL_PWR_GPIO_BIT_4
1094 * @arg @ref LL_PWR_GPIO_BIT_5
1095 * @arg @ref LL_PWR_GPIO_BIT_6
1096 * @arg @ref LL_PWR_GPIO_BIT_7
1097 * @arg @ref LL_PWR_GPIO_BIT_8
1098 * @arg @ref LL_PWR_GPIO_BIT_9
1099 * @arg @ref LL_PWR_GPIO_BIT_10
1100 * @arg @ref LL_PWR_GPIO_BIT_11
1101 * @arg @ref LL_PWR_GPIO_BIT_12
1102 * @arg @ref LL_PWR_GPIO_BIT_13
1103 * @arg @ref LL_PWR_GPIO_BIT_14
1104 * @arg @ref LL_PWR_GPIO_BIT_15
1105 * @retval None
1106 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1107 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1108 {
1109 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1110 }
1111
1112 /**
1113 * @brief Check if GPIO pull-up state is enabled
1114 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1115 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1116 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1117 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1118 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1119 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1120 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1121 * @param GPIO This parameter can be one of the following values:
1122 * @arg @ref LL_PWR_GPIO_A
1123 * @arg @ref LL_PWR_GPIO_B
1124 * @arg @ref LL_PWR_GPIO_C
1125 * @arg @ref LL_PWR_GPIO_D
1126 * @arg @ref LL_PWR_GPIO_E
1127 * @arg @ref LL_PWR_GPIO_F
1128 * @arg @ref LL_PWR_GPIO_G
1129 *
1130 * (*) value not defined in all devices
1131 * @param GPIONumber This parameter can be one of the following values:
1132 * @arg @ref LL_PWR_GPIO_BIT_0
1133 * @arg @ref LL_PWR_GPIO_BIT_1
1134 * @arg @ref LL_PWR_GPIO_BIT_2
1135 * @arg @ref LL_PWR_GPIO_BIT_3
1136 * @arg @ref LL_PWR_GPIO_BIT_4
1137 * @arg @ref LL_PWR_GPIO_BIT_5
1138 * @arg @ref LL_PWR_GPIO_BIT_6
1139 * @arg @ref LL_PWR_GPIO_BIT_7
1140 * @arg @ref LL_PWR_GPIO_BIT_8
1141 * @arg @ref LL_PWR_GPIO_BIT_9
1142 * @arg @ref LL_PWR_GPIO_BIT_10
1143 * @arg @ref LL_PWR_GPIO_BIT_11
1144 * @arg @ref LL_PWR_GPIO_BIT_12
1145 * @arg @ref LL_PWR_GPIO_BIT_13
1146 * @arg @ref LL_PWR_GPIO_BIT_14
1147 * @arg @ref LL_PWR_GPIO_BIT_15
1148 * @retval State of bit (1 or 0).
1149 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1150 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1151 {
1152 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1153 }
1154
1155 /**
1156 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1157 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1158 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1159 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1160 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1161 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1162 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1163 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1164 * @param GPIO This parameter can be one of the following values:
1165 * @arg @ref LL_PWR_GPIO_A
1166 * @arg @ref LL_PWR_GPIO_B
1167 * @arg @ref LL_PWR_GPIO_C
1168 * @arg @ref LL_PWR_GPIO_D
1169 * @arg @ref LL_PWR_GPIO_E
1170 * @arg @ref LL_PWR_GPIO_F
1171 * @arg @ref LL_PWR_GPIO_G
1172 *
1173 * (*) value not defined in all devices
1174 * @param GPIONumber This parameter can be one of the following values:
1175 * @arg @ref LL_PWR_GPIO_BIT_0
1176 * @arg @ref LL_PWR_GPIO_BIT_1
1177 * @arg @ref LL_PWR_GPIO_BIT_2
1178 * @arg @ref LL_PWR_GPIO_BIT_3
1179 * @arg @ref LL_PWR_GPIO_BIT_4
1180 * @arg @ref LL_PWR_GPIO_BIT_5
1181 * @arg @ref LL_PWR_GPIO_BIT_6
1182 * @arg @ref LL_PWR_GPIO_BIT_7
1183 * @arg @ref LL_PWR_GPIO_BIT_8
1184 * @arg @ref LL_PWR_GPIO_BIT_9
1185 * @arg @ref LL_PWR_GPIO_BIT_10
1186 * @arg @ref LL_PWR_GPIO_BIT_11
1187 * @arg @ref LL_PWR_GPIO_BIT_12
1188 * @arg @ref LL_PWR_GPIO_BIT_13
1189 * @arg @ref LL_PWR_GPIO_BIT_14
1190 * @arg @ref LL_PWR_GPIO_BIT_15
1191 * @retval None
1192 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1193 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1194 {
1195 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1196 }
1197
1198 /**
1199 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1200 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1201 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1202 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1203 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1204 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1205 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1206 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1207 * @param GPIO This parameter can be one of the following values:
1208 * @arg @ref LL_PWR_GPIO_A
1209 * @arg @ref LL_PWR_GPIO_B
1210 * @arg @ref LL_PWR_GPIO_C
1211 * @arg @ref LL_PWR_GPIO_D
1212 * @arg @ref LL_PWR_GPIO_E
1213 * @arg @ref LL_PWR_GPIO_F
1214 * @arg @ref LL_PWR_GPIO_G
1215 *
1216 * (*) value not defined in all devices
1217 * @param GPIONumber This parameter can be one of the following values:
1218 * @arg @ref LL_PWR_GPIO_BIT_0
1219 * @arg @ref LL_PWR_GPIO_BIT_1
1220 * @arg @ref LL_PWR_GPIO_BIT_2
1221 * @arg @ref LL_PWR_GPIO_BIT_3
1222 * @arg @ref LL_PWR_GPIO_BIT_4
1223 * @arg @ref LL_PWR_GPIO_BIT_5
1224 * @arg @ref LL_PWR_GPIO_BIT_6
1225 * @arg @ref LL_PWR_GPIO_BIT_7
1226 * @arg @ref LL_PWR_GPIO_BIT_8
1227 * @arg @ref LL_PWR_GPIO_BIT_9
1228 * @arg @ref LL_PWR_GPIO_BIT_10
1229 * @arg @ref LL_PWR_GPIO_BIT_11
1230 * @arg @ref LL_PWR_GPIO_BIT_12
1231 * @arg @ref LL_PWR_GPIO_BIT_13
1232 * @arg @ref LL_PWR_GPIO_BIT_14
1233 * @arg @ref LL_PWR_GPIO_BIT_15
1234 * @retval None
1235 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1236 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1237 {
1238 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1239 }
1240
1241 /**
1242 * @brief Check if GPIO pull-down state is enabled
1243 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1244 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1245 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1246 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1247 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1248 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1249 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1250 * @param GPIO This parameter can be one of the following values:
1251 * @arg @ref LL_PWR_GPIO_A
1252 * @arg @ref LL_PWR_GPIO_B
1253 * @arg @ref LL_PWR_GPIO_C
1254 * @arg @ref LL_PWR_GPIO_D
1255 * @arg @ref LL_PWR_GPIO_E
1256 * @arg @ref LL_PWR_GPIO_F
1257 * @arg @ref LL_PWR_GPIO_G
1258 *
1259 * (*) value not defined in all devices
1260 * @param GPIONumber This parameter can be one of the following values:
1261 * @arg @ref LL_PWR_GPIO_BIT_0
1262 * @arg @ref LL_PWR_GPIO_BIT_1
1263 * @arg @ref LL_PWR_GPIO_BIT_2
1264 * @arg @ref LL_PWR_GPIO_BIT_3
1265 * @arg @ref LL_PWR_GPIO_BIT_4
1266 * @arg @ref LL_PWR_GPIO_BIT_5
1267 * @arg @ref LL_PWR_GPIO_BIT_6
1268 * @arg @ref LL_PWR_GPIO_BIT_7
1269 * @arg @ref LL_PWR_GPIO_BIT_8
1270 * @arg @ref LL_PWR_GPIO_BIT_9
1271 * @arg @ref LL_PWR_GPIO_BIT_10
1272 * @arg @ref LL_PWR_GPIO_BIT_11
1273 * @arg @ref LL_PWR_GPIO_BIT_12
1274 * @arg @ref LL_PWR_GPIO_BIT_13
1275 * @arg @ref LL_PWR_GPIO_BIT_14
1276 * @arg @ref LL_PWR_GPIO_BIT_15
1277 * @retval State of bit (1 or 0).
1278 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1279 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1280 {
1281 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1282 }
1283
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1289 * @{
1290 */
1291
1292 /**
1293 * @brief Get Internal Wake-up line Flag
1294 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1295 * @retval State of bit (1 or 0).
1296 */
LL_PWR_IsActiveFlag_InternWU(void)1297 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1298 {
1299 uint32_t temp;
1300 temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
1301
1302 return ((temp == (PWR_SR1_WUFI))?1U:0U);
1303
1304 }
1305
1306 /**
1307 * @brief Get Stand-By Flag
1308 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1309 * @retval State of bit (1 or 0).
1310 */
LL_PWR_IsActiveFlag_SB(void)1311 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1312 {
1313 uint32_t temp;
1314 temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
1315
1316 return ((temp == (PWR_SR1_SBF))?1U:0U);
1317
1318 }
1319
1320 /**
1321 * @brief Get Wake-up Flag 5
1322 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1323 * @retval State of bit (1 or 0).
1324 */
LL_PWR_IsActiveFlag_WU5(void)1325 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1326 {
1327 uint32_t temp;
1328 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
1329
1330 return ((temp == (PWR_SR1_WUF5))?1U:0U);
1331 }
1332
1333 /**
1334 * @brief Get Wake-up Flag 4
1335 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1336 * @retval State of bit (1 or 0).
1337 */
LL_PWR_IsActiveFlag_WU4(void)1338 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1339 {
1340 uint32_t temp;
1341 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
1342
1343 return ((temp == (PWR_SR1_WUF4))?1U:0U);
1344 }
1345
1346 /**
1347 * @brief Get Wake-up Flag 3
1348 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1349 * @retval State of bit (1 or 0).
1350 */
LL_PWR_IsActiveFlag_WU3(void)1351 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1352 {
1353 uint32_t temp;
1354 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
1355
1356 return ((temp == (PWR_SR1_WUF3))?1U:0U);
1357 }
1358
1359 /**
1360 * @brief Get Wake-up Flag 2
1361 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1362 * @retval State of bit (1 or 0).
1363 */
LL_PWR_IsActiveFlag_WU2(void)1364 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1365 {
1366 uint32_t temp;
1367 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
1368
1369 return ((temp == (PWR_SR1_WUF2))?1U:0U);
1370 }
1371
1372 /**
1373 * @brief Get Wake-up Flag 1
1374 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1375 * @retval State of bit (1 or 0).
1376 */
LL_PWR_IsActiveFlag_WU1(void)1377 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1378 {
1379 uint32_t temp;
1380 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
1381
1382 return ((temp == (PWR_SR1_WUF1))?1U:0U);
1383 }
1384
1385 /**
1386 * @brief Clear Stand-By Flag
1387 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1388 * @retval None
1389 */
LL_PWR_ClearFlag_SB(void)1390 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1391 {
1392 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1393 }
1394
1395 /**
1396 * @brief Clear Wake-up Flags
1397 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1398 * @retval None
1399 */
LL_PWR_ClearFlag_WU(void)1400 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1401 {
1402 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1403 }
1404
1405 /**
1406 * @brief Clear Wake-up Flag 5
1407 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1408 * @retval None
1409 */
LL_PWR_ClearFlag_WU5(void)1410 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1411 {
1412 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1413 }
1414
1415 /**
1416 * @brief Clear Wake-up Flag 4
1417 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1418 * @retval None
1419 */
LL_PWR_ClearFlag_WU4(void)1420 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1421 {
1422 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1423 }
1424
1425 /**
1426 * @brief Clear Wake-up Flag 3
1427 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1428 * @retval None
1429 */
LL_PWR_ClearFlag_WU3(void)1430 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1431 {
1432 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1433 }
1434
1435 /**
1436 * @brief Clear Wake-up Flag 2
1437 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1438 * @retval None
1439 */
LL_PWR_ClearFlag_WU2(void)1440 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1441 {
1442 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1443 }
1444
1445 /**
1446 * @brief Clear Wake-up Flag 1
1447 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1448 * @retval None
1449 */
LL_PWR_ClearFlag_WU1(void)1450 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1451 {
1452 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1453 }
1454
1455 /**
1456 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1457 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1458 * @retval State of bit (1 or 0).
1459 */
LL_PWR_IsActiveFlag_PVMO4(void)1460 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1461 {
1462 uint32_t temp;
1463 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
1464
1465 return ((temp == (PWR_SR2_PVMO4))?1U:0U);
1466
1467 }
1468
1469 /**
1470 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1471 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1472 * @retval State of bit (1 or 0).
1473 */
LL_PWR_IsActiveFlag_PVMO3(void)1474 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1475 {
1476 uint32_t temp;
1477 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
1478
1479 return ((temp == (PWR_SR2_PVMO3))?1U:0U);
1480
1481 }
1482
1483 #if defined(PWR_SR2_PVMO2)
1484 /**
1485 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1486 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1487 * @retval State of bit (1 or 0).
1488 */
LL_PWR_IsActiveFlag_PVMO2(void)1489 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1490 {
1491 uint32_t temp;
1492 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
1493
1494 return ((temp == (PWR_SR2_PVMO2))?1U:0U);
1495
1496 }
1497 #endif /* PWR_SR2_PVMO2 */
1498
1499 #if defined(PWR_SR2_PVMO1)
1500 /**
1501 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1502 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1503 * @retval State of bit (1 or 0).
1504 */
LL_PWR_IsActiveFlag_PVMO1(void)1505 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1506 {
1507 uint32_t temp;
1508 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
1509
1510 return ((temp == (PWR_SR2_PVMO1))?1U:0U);
1511
1512 }
1513 #endif /* PWR_SR2_PVMO1 */
1514
1515 /**
1516 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1517 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1518 * @retval State of bit (1 or 0).
1519 */
LL_PWR_IsActiveFlag_PVDO(void)1520 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1521 {
1522 uint32_t temp;
1523 temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
1524
1525 return ((temp == (PWR_SR2_PVDO))?1U:0U);
1526
1527 }
1528
1529 /**
1530 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1531 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1532 * @retval State of bit (1 or 0).
1533 */
LL_PWR_IsActiveFlag_VOS(void)1534 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1535 {
1536 uint32_t temp;
1537 temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
1538
1539 return ((temp == (PWR_SR2_VOSF))?1U:0U);
1540
1541 }
1542
1543 /**
1544 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1545 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1546 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1547 * @retval State of bit (1 or 0).
1548 */
LL_PWR_IsActiveFlag_REGLPF(void)1549 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1550 {
1551 uint32_t temp;
1552 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
1553
1554 return ((temp == (PWR_SR2_REGLPF))?1U:0U);
1555
1556 }
1557
1558 /**
1559 * @brief Indicate whether or not the low-power regulator is ready
1560 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1561 * @retval State of bit (1 or 0).
1562 */
LL_PWR_IsActiveFlag_REGLPS(void)1563 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1564 {
1565 uint32_t temp;
1566 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
1567
1568 return ((temp == (PWR_SR2_REGLPS))?1U:0U);
1569
1570 }
1571
1572 /**
1573 * @}
1574 */
1575
1576 #if defined(USE_FULL_LL_DRIVER)
1577 /** @defgroup PWR_LL_EF_Init De-initialization function
1578 * @{
1579 */
1580 ErrorStatus LL_PWR_DeInit(void);
1581 /**
1582 * @}
1583 */
1584 #endif /* USE_FULL_LL_DRIVER */
1585
1586 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1587 * @{
1588 */
1589 /* Old functions name kept for legacy purpose, to be replaced by the */
1590 /* current functions name. */
1591 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1592 #define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
1593 #define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
1594 #define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
1595 #define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
1596 #define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
1597
1598 /**
1599 * @}
1600 */
1601
1602 /**
1603 * @}
1604 */
1605
1606 /**
1607 * @}
1608 */
1609
1610 #endif /* defined(PWR) */
1611
1612 /**
1613 * @}
1614 */
1615
1616 #ifdef __cplusplus
1617 }
1618 #endif
1619
1620 #endif /* STM32G4xx_LL_PWR_H */
1621
1622 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1623