/dports/emulators/mess/mame-mame0226/src/devices/cpu/alto2/ |
H A D | a2ram.cpp | 167 LOG((this,LOG_RAM,2," <-S%02o; bus &= S[%o][%02o] (%#o)\n", rsel(), bank, rsel(), r)); in bs_early_read_sreg() 170 LOG((this,LOG_RAM,2," <-S%02o; bus &= M (%#o)\n", rsel(), r)); in bs_early_read_sreg() 181 LOG((this,LOG_RAM,2," S%02o<- BUS &= garbage (%#o)\n", rsel(), r)); in bs_early_load_sreg() 192 LOG((this,LOG_RAM,2," S%02o<- S[%o][%02o] := %#o\n", rsel(), bank, rsel(), m_myl)); in bs_late_load_sreg() 205 LOG((this,LOG_RAM,2," SWMODE: branch from %s to ROM%d (%#o)\n", from, page, m_next2)); in branch_ROM() 218 LOG((this,LOG_RAM,2," SWMODE: branch from %s to RAM%d\n", from, page, m_next2)); in branch_RAM() 389 LOG((this,LOG_RAM,2," WRTRAM\n")); in f1_late_wrtram() 398 LOG((this,LOG_RAM,2," RDRAM\n")); in f1_late_rdram() 410 LOG((this,LOG_RAM,2," RMR<-; BUS (%#o)\n", m_bus)); in f1_late_load_rmr() 422 LOG((this,LOG_RAM,2," SRB<-; srb[%d] := %#o\n", m_task, m_s_reg_bank[m_task])); in f1_late_load_srb()
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H A D | alto2cpu.h | 114 LOG_RAM = (1 << 18), enumerator
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/alto2/ |
H A D | a2ram.cpp | 167 LOG((this,LOG_RAM,2," <-S%02o; bus &= S[%o][%02o] (%#o)\n", rsel(), bank, rsel(), r)); in bs_early_read_sreg() 170 LOG((this,LOG_RAM,2," <-S%02o; bus &= M (%#o)\n", rsel(), r)); in bs_early_read_sreg() 181 LOG((this,LOG_RAM,2," S%02o<- BUS &= garbage (%#o)\n", rsel(), r)); in bs_early_load_sreg() 192 LOG((this,LOG_RAM,2," S%02o<- S[%o][%02o] := %#o\n", rsel(), bank, rsel(), m_myl)); in bs_late_load_sreg() 205 LOG((this,LOG_RAM,2," SWMODE: branch from %s to ROM%d (%#o)\n", from, page, m_next2)); in branch_ROM() 218 LOG((this,LOG_RAM,2," SWMODE: branch from %s to RAM%d\n", from, page, m_next2)); in branch_RAM() 389 LOG((this,LOG_RAM,2," WRTRAM\n")); in f1_late_wrtram() 398 LOG((this,LOG_RAM,2," RDRAM\n")); in f1_late_rdram() 410 LOG((this,LOG_RAM,2," RMR<-; BUS (%#o)\n", m_bus)); in f1_late_load_rmr() 422 LOG((this,LOG_RAM,2," SRB<-; srb[%d] := %#o\n", m_task, m_s_reg_bank[m_task])); in f1_late_load_srb()
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H A D | alto2cpu.h | 114 LOG_RAM = (1 << 18), enumerator
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/dports/emulators/mess/mame-mame0226/src/devices/bus/hexbus/ |
H A D | hx5102.cpp | 84 #define LOG_RAM (1U<<7) // RAM macro 204 LOGMASKED(LOG_RAM, "RAM %04x -> %02x\n", (offset & 0x07ff)|0xe000, val); in read() 212 LOGMASKED(LOG_RAM, "RAM %04x -> %02x\n", (offset & 0x07ff)|0xe800, val); in read() 260 LOGMASKED(LOG_RAM, "RAM %04x <- %02x\n", (offset & 0x07ff)|0xe000, data); in write() 268 LOGMASKED(LOG_RAM, "RAM %04x <- %02x\n", (offset & 0x07ff)|0xe800, data); in write()
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/dports/emulators/mame/mame-mame0226/src/devices/bus/hexbus/ |
H A D | hx5102.cpp | 84 #define LOG_RAM (1U<<7) // RAM macro 204 LOGMASKED(LOG_RAM, "RAM %04x -> %02x\n", (offset & 0x07ff)|0xe000, val); in read() 212 LOGMASKED(LOG_RAM, "RAM %04x -> %02x\n", (offset & 0x07ff)|0xe800, val); in read() 260 LOGMASKED(LOG_RAM, "RAM %04x <- %02x\n", (offset & 0x07ff)|0xe000, data); in write() 268 LOGMASKED(LOG_RAM, "RAM %04x <- %02x\n", (offset & 0x07ff)|0xe800, data); in write()
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/dports/emulators/mess/mame-mame0226/src/devices/bus/ti99/peb/ |
H A D | pgram.cpp | 122 #define LOG_RAM (1U<<4) macro 265 …LOGMASKED(LOG_RAM, "%04x (bank %d) -> %04x\n",(offset&0xfffe)|0x4000, m_bankff->output_r()? 1:0, b… in dsr_ram_read() 304 LOGMASKED(LOG_RAM, "%04x (bank %d) <- %02x\n", offset|0x4000, m_bankff->output_r()? 1:0, data); in dsr_ram_write()
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H A D | myarcfdc.cpp | 35 #define LOG_RAM (1U<<5) // Access to SRAM macro 142 LOGMASKED(LOG_RAM, "Read RAM: %04x -> %02x\n", m_address & 0xffff, *value); in readz() 181 LOGMASKED(LOG_RAM, "Write RAM: %04x <- %02x\n", m_address & 0xffff, data); in write()
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H A D | cc_fdc.cpp | 39 #define LOG_RAM (1U<<5) // Access to SRAM macro 209 LOGMASKED(LOG_RAM, "Read RAM: %04x -> %02x\n", m_address & 0xffff, *value); in readz() 244 LOGMASKED(LOG_RAM, "Write RAM: %04x <- %02x\n", m_address & 0xffff, data&0xf0); in write()
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H A D | hfdc.cpp | 65 #define LOG_RAM (1U<<4) macro 251 LOGMASKED(LOG_RAM, "%04x[%02x] -> %04x\n", m_address & 0xffff, m_ram_page[bank], valword); in readz() 318 LOGMASKED(LOG_RAM, "%04x[%02x] <- %02x\n", m_address & 0xffff, m_ram_page[bank], data); in write()
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/dports/emulators/mame/mame-mame0226/src/devices/bus/ti99/peb/ |
H A D | pgram.cpp | 122 #define LOG_RAM (1U<<4) macro 265 …LOGMASKED(LOG_RAM, "%04x (bank %d) -> %04x\n",(offset&0xfffe)|0x4000, m_bankff->output_r()? 1:0, b… in dsr_ram_read() 304 LOGMASKED(LOG_RAM, "%04x (bank %d) <- %02x\n", offset|0x4000, m_bankff->output_r()? 1:0, data); in dsr_ram_write()
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H A D | myarcfdc.cpp | 35 #define LOG_RAM (1U<<5) // Access to SRAM macro 142 LOGMASKED(LOG_RAM, "Read RAM: %04x -> %02x\n", m_address & 0xffff, *value); in readz() 181 LOGMASKED(LOG_RAM, "Write RAM: %04x <- %02x\n", m_address & 0xffff, data); in write()
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H A D | cc_fdc.cpp | 39 #define LOG_RAM (1U<<5) // Access to SRAM macro 209 LOGMASKED(LOG_RAM, "Read RAM: %04x -> %02x\n", m_address & 0xffff, *value); in readz() 244 LOGMASKED(LOG_RAM, "Write RAM: %04x <- %02x\n", m_address & 0xffff, data&0xf0); in write()
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H A D | hfdc.cpp | 65 #define LOG_RAM (1U<<4) macro 251 LOGMASKED(LOG_RAM, "%04x[%02x] -> %04x\n", m_address & 0xffff, m_ram_page[bank], valword); in readz() 318 LOGMASKED(LOG_RAM, "%04x[%02x] <- %02x\n", m_address & 0xffff, m_ram_page[bank], data); in write()
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/dports/emulators/mess/mame-mame0226/src/mame/machine/ |
H A D | iteagle_fpga.cpp | 10 #define LOG_RAM (0) macro 637 if (LOG_RAM) in e1_nvram_r() 645 if (LOG_RAM) in e1_nvram_w() 654 if (LOG_RAM) in e1_ram_r() 662 if (LOG_RAM) in e1_ram_w()
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H A D | cdicdic.cpp | 39 #define LOG_RAM (1 << 9) macro 40 …_SAMPLES | LOG_COMMANDS | LOG_SECTORS | LOG_IRQS | LOG_READS | LOG_WRITES | LOG_UNKNOWNS | LOG_RAM) 1359 …LOGMASKED(LOG_RAM, "%s: ram_w: %04x = %04x & %04x\n", machine().describe_context(), offset << 1, d… in ram_w() 1365 …LOGMASKED(LOG_RAM, "%s: ram_r: %04x : %04x & %04x\n", machine().describe_context(), offset << 1, m… in ram_r()
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H A D | rmnimbus.cpp | 132 #define LOG_RAM 0 macro 940 if(LOG_RAM) logerror("mapped %s",bank); in nimbus_bank_memory() 954 if(LOG_RAM) logerror("NOP\n"); in nimbus_bank_memory()
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/dports/emulators/mame/mame-mame0226/src/mame/machine/ |
H A D | iteagle_fpga.cpp | 10 #define LOG_RAM (0) macro 637 if (LOG_RAM) in e1_nvram_r() 645 if (LOG_RAM) in e1_nvram_w() 654 if (LOG_RAM) in e1_ram_r() 662 if (LOG_RAM) in e1_ram_w()
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H A D | cdicdic.cpp | 39 #define LOG_RAM (1 << 9) macro 40 …_SAMPLES | LOG_COMMANDS | LOG_SECTORS | LOG_IRQS | LOG_READS | LOG_WRITES | LOG_UNKNOWNS | LOG_RAM) 1359 …LOGMASKED(LOG_RAM, "%s: ram_w: %04x = %04x & %04x\n", machine().describe_context(), offset << 1, d… in ram_w() 1365 …LOGMASKED(LOG_RAM, "%s: ram_r: %04x : %04x & %04x\n", machine().describe_context(), offset << 1, m… in ram_r()
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H A D | rmnimbus.cpp | 132 #define LOG_RAM 0 macro 940 if(LOG_RAM) logerror("mapped %s",bank); in nimbus_bank_memory() 954 if(LOG_RAM) logerror("NOP\n"); in nimbus_bank_memory()
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/dports/emulators/mess/mame-mame0226/src/mame/drivers/ |
H A D | myb3k.cpp | 61 #define LOG_RAM (1U << 13) macro 80 #define LOGRAM(...) LOGMASKED(LOG_RAM, __VA_ARGS__)
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/dports/emulators/mame/mame-mame0226/src/mame/drivers/ |
H A D | myb3k.cpp | 61 #define LOG_RAM (1U << 13) macro 80 #define LOGRAM(...) LOGMASKED(LOG_RAM, __VA_ARGS__)
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