/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument 802 switch (LdSt.getOpcode()) { in getMemOperandWithOffset() 815 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument 802 switch (LdSt.getOpcode()) { in getMemOperandWithOffset() 815 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 56 def LdSt : ProcResource<1> { let BufferSize = 0; } 65 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 68 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 56 def LdSt : ProcResource<1> { let BufferSize = 0; } 65 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 68 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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H A D | LanaiInstrInfo.cpp | 754 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth() argument 758 if (LdSt.getNumOperands() != 4) in getMemOpBaseRegImmOfsWidth() 760 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOpBaseRegImmOfsWidth() 761 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOpBaseRegImmOfsWidth() 764 switch (LdSt.getOpcode()) { in getMemOpBaseRegImmOfsWidth() 785 BaseReg = LdSt.getOperand(1).getReg(); in getMemOpBaseRegImmOfsWidth() 786 Offset = LdSt.getOperand(2).getImm(); in getMemOpBaseRegImmOfsWidth() 791 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs() argument 793 switch (LdSt.getOpcode()) { in getMemOpBaseRegImmOfs() 806 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
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