| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Mips/ |
| H A D | MipsSchedBeri.td | 6 // LoadLatency seems to be include the one cycle for the instruction -> set to 3
7 let LoadLatency = 3;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
629 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
647 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
672 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
783 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1400 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
629 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
647 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
672 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
783 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1400 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
629 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
647 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
672 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
783 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1400 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
629 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
647 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
672 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
783 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1400 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
629 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
647 let Latency = !add(Znver3Model.LoadLatency, Zn3MULX64rr.Latency);
672 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
783 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1400 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 48 let LoadLatency = 4;
453 Znver3Model.LoadLatency,
480 def : ReadAdvance<ReadAfterLd, Znver3Model.LoadLatency>;
503 let Latency = !add(Znver3Model.LoadLatency, 1);
517 let Latency = Znver3Model.LoadLatency;
645 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
756 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
1228 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
1359 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMPSYrr.Latency);
1373 let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
[all …]
|
| /dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/ARM/ |
| H A D | ARMScheduleM3.td | 17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
|
| /dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/ |
| H A D | ARMScheduleM3.td | 17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
|
| /dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/ARM/ |
| H A D | ARMScheduleM3.td | 17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMScheduleM3.td | 17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMScheduleM3.td | 17 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/M68k/ |
| H A D | M68kSchedule.td | 17 let LoadLatency = 4; // Word (Rn)
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 31 let LoadLatency = 1;
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 31 let LoadLatency = 1;
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 30 let LoadLatency = 1;
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 30 let LoadLatency = 1;
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 30 let LoadLatency = 1;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 30 let LoadLatency = 1;
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonScheduleV62.td | 30 let LoadLatency = 1;
|