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Searched refs:LowerToPredicatedOp (Results 1 – 22 of 22) sorted by relevance

/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3309 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3436 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4783 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4839 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4842 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4845 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4848 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4939 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4951 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
10582 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
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H A DAArch64ISelLowering.h955 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3309 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3436 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4783 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4839 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4842 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4845 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4848 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4939 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4951 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
10582 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
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H A DAArch64ISelLowering.h955 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3309 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3436 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4783 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4839 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4842 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4845 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4848 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4939 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4951 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
10582 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h955 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3337 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3510 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4867 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FADD_PRED); in LowerOperation()
4869 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FSUB_PRED); in LowerOperation()
4871 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMUL_PRED); in LowerOperation()
4873 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
5028 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
5040 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
5044 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SUB_PRED); in LowerOperation()
10815 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h965 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3309 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3436 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4783 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4839 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4842 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4845 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4848 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4939 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4951 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
10582 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h955 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3309 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3436 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4783 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4839 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4842 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4845 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4848 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4939 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4951 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
10582 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h955 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3126 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3212 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4271 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4327 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4330 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4333 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4336 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4415 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4425 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
9985 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h906 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3126 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3212 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
4271 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4327 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4330 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4333 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4336 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4415 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4425 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
9985 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h906 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3024 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorFP_TO_INT()
3108 return LowerToPredicatedOp(Op, DAG, Opcode); in LowerVectorINT_TO_FP()
3975 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
4033 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED, in LowerOperation()
4036 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_PRED, in LowerOperation()
4039 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_PRED, in LowerOperation()
4042 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_PRED, in LowerOperation()
4119 return LowerToPredicatedOp(Op, DAG, in LowerOperation()
4129 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
9570 return LowerToPredicatedOp(Op, DAG, PredOpcode); in LowerDIV()
[all …]
H A DAArch64ISelLowering.h893 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, unsigned NewOp,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h866 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
H A DAArch64ISelLowering.cpp3471 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FADD_PRED); in LowerOperation()
3478 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
3509 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SDIV_PRED); in LowerOperation()
3511 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UDIV_PRED); in LowerOperation()
3513 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_MERGE_OP1); in LowerOperation()
3515 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_MERGE_OP1); in LowerOperation()
3517 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_MERGE_OP1); in LowerOperation()
3519 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_MERGE_OP1); in LowerOperation()
3583 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
8954 return LowerToPredicatedOp(Op, DAG, Opc); in LowerVectorSRA_SRL_SHL()
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.h861 SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
H A DAArch64ISelLowering.cpp3475 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FADD_PRED); in LowerOperation()
3482 return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED); in LowerOperation()
3513 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SDIV_PRED); in LowerOperation()
3515 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UDIV_PRED); in LowerOperation()
3517 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_MERGE_OP1); in LowerOperation()
3519 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMIN_MERGE_OP1); in LowerOperation()
3521 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMAX_MERGE_OP1); in LowerOperation()
3523 return LowerToPredicatedOp(Op, DAG, AArch64ISD::UMAX_MERGE_OP1); in LowerOperation()
3587 return LowerToPredicatedOp(Op, DAG, AArch64ISD::ADD_PRED); in LowerOperation()
8985 return LowerToPredicatedOp(Op, DAG, Opc); in LowerVectorSRA_SRL_SHL()
[all …]