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/dports/lang/v8/v8-9.6.180.12/test/unittests/base/
H A Ddivision-by-constant-unittest.cc29 using M64 = MagicNumbersForDivision<uint64_t>; typedef
36 static M64 s64(int64_t d) { in s64()
100 EXPECT_EQ(M64(0x5555555555555556ULL, 0, false), s64(3)); in TEST()
101 EXPECT_EQ(M64(0x6666666666666667ULL, 1, false), s64(5)); in TEST()
102 EXPECT_EQ(M64(0x2AAAAAAAAAAAAAABULL, 0, false), s64(6)); in TEST()
103 EXPECT_EQ(M64(0x4924924924924925ULL, 1, false), s64(7)); in TEST()
104 EXPECT_EQ(M64(0x1C71C71C71C71C72ULL, 0, false), s64(9)); in TEST()
115 EXPECT_EQ(M64(0x0000000000000000ULL, 0, true), u64(1)); in TEST()
119 EXPECT_EQ(M64(0xAAAAAAAAAAAAAAABULL, 1, false), u64(3)); in TEST()
120 EXPECT_EQ(M64(0xCCCCCCCCCCCCCCCDULL, 2, false), u64(5)); in TEST()
[all …]
/dports/lang/zig-devel/zig-0.9.0/lib/libc/include/any-windows-any/
H A Divec.h32 class M64
37 M64() {} in M64() function
38 M64(__m64 mm) { vec = mm; } in M64() function
39 M64(__int64 mm) { _MM_QW = mm; } in M64() function
40 M64(int i) { vec = _m_from_int(i); } in M64() function
44 M64& operator&=(const M64 &a) { return *this = (M64) _m_pand(vec,a); }
45 M64& operator|=(const M64 &a) { return *this = (M64) _m_por(vec,a); }
46 M64& operator^=(const M64 &a) { return *this = (M64) _m_pxor(vec,a); }
/dports/lang/zig/zig-0.9.0/lib/libc/include/any-windows-any/
H A Divec.h32 class M64
37 M64() {} in M64() function
38 M64(__m64 mm) { vec = mm; } in M64() function
39 M64(__int64 mm) { _MM_QW = mm; } in M64() function
40 M64(int i) { vec = _m_from_int(i); } in M64() function
44 M64& operator&=(const M64 &a) { return *this = (M64) _m_pand(vec,a); }
45 M64& operator|=(const M64 &a) { return *this = (M64) _m_por(vec,a); }
46 M64& operator^=(const M64 &a) { return *this = (M64) _m_pxor(vec,a); }
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/
H A Dwin64_alloca_dynalloca.ll9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
41 ; M64: andq $-16, %rax
43 ; M64: subq %rax, %rsp
44 ; M64: movq %rsp, %rax
67 ; M64: subq $48, %rsp
70 ; M64: callq bar
91 ; M64-LABEL: aligned:
[all …]
/dports/math/polymake/polymake-4.5/apps/common/cpperl/
H A Dauto-monomial.cpperl3 …/Polynomial.h", "polymake/Rational.h"], "kind": "stat", "sig": "Polynomial::monomial:M64.Int.Int"},
4 …Rational.h", "polymake/RationalFunction.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
5 …Rational.h", "polymake/RationalFunction.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
6 …alFunction.h", "polymake/TropicalNumber.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
7 …Rational.h", "polymake/RationalFunction.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
8 …ional.h", "polymake/TropicalNumber.h"], "kind": "stat", "sig": "Polynomial::monomial:M64.Int.Int"},
9 …alFunction.h", "polymake/TropicalNumber.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
10 …alFunction.h", "polymake/TropicalNumber.h"], "kind": "stat", "sig": "UniPolynomial::monomial:M64"},
11 …ional.h", "polymake/TropicalNumber.h"], "kind": "stat", "sig": "Polynomial::monomial:M64.Int.Int"},
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]
/dports/lang/clover/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_ops.c204 #define M64 midgard_reg_mode_64 macro
234 … [midgard_op_atomic_add64] = {"AADD.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
235 … [midgard_op_atomic_and64] = {"AAND.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
236 … [midgard_op_atomic_or64] = {"AOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
237 … [midgard_op_atomic_xor64] = {"AXOR.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
238 … [midgard_op_atomic_imin64] = {"AMIN.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
239 … [midgard_op_atomic_umin64] = {"AMIN.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
240 … [midgard_op_atomic_imax64] = {"AMAX.s64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
241 … [midgard_op_atomic_umax64] = {"AMAX.u64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
242 … [midgard_op_atomic_xchg64] = {"XCHG.64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOMIC},
[all …]

12345678910>>...30