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/dports/devel/plan9port/plan9port-1f098efb7370a0b28306d10681e21883fb1c1507/lp/process/
H A Dg3post75 if (~ $MAG '') MAG=1
76 if (~ $MAG [.0-9]*) MAG=-m^$MAG^,^`{echo $MAG '*' 2 | hoc}
81 g3p9bit | p9bitpost $MAG $LAND $PATCH | $LPLIB/process/hpost
H A Dp9bitpost77 if (! ~ $MAG '') MAG=-m^$MAG
78 if (~ $MAG '') MAG=()
82 p9bitpost $MAG $LAND $PATCH | $LPLIB/process/hpost
H A Djpgpost75 if (~ $MAG '') MAG=1
76 if (~ $MAG [.0-9]*) MAG=-m^$MAG
81 9 jpg -t9 | p9bitpost $MAG $LAND $PATCH -p 32 26.17 | $LPLIB/process/hpost
H A Dgifpost75 if (~ $MAG '') MAG=1
76 if (~ $MAG [.0-9]*) MAG=-m^$MAG
81 /$cputype/bin/gif -t | /$cputype/bin/aux/p9bitpost $MAG $LAND $PATCH | $LPLIB/process/hpost
H A Dtr2post81 if (! ~ $MAG '' -m*) MAG=-m^$MAG
85 eval tr2post $XOFF $YOFF $COPIES $MAG $NPAG $LAND $OLIST $PATCH | $LPLIB/process/hpost
/dports/cad/ghdl/ghdl-1.0.0/libraries/ieee/
H A Dmath_complex.vhdl167 -- result.MAG >= 0.0
212 -- ABS(Z) = Z.MAG
271 -- result.MAG >= 0.0
301 -- result.MAG >= 0.0
334 -- result.MAG >= 0.0
446 -- Z.MAG /= 0.0
466 -- Z.MAG /= 0.0
486 -- Z.MAG /= 0.0
525 -- Z.MAG /= 0.0
1038 -- R.MAG > 0.0
[all …]
H A Dmath_complex-body.vhdl81 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
86 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
117 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
122 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
217 return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
1359 ZOUT.MAG := L.MAG * R.MAG;
1390 ZOUT.MAG := ZL.MAG * R.MAG;
1421 ZOUT.MAG := L.MAG * ZR.MAG;
1520 ZOUT.MAG := L.MAG/R.MAG;
1558 ZOUT.MAG := L.MAG/ZR.MAG;
[all …]
/dports/cad/ghdl/ghdl-1.0.0/libraries/ieee2008/
H A Dmath_complex.vhdl167 -- result.MAG >= 0.0
212 -- ABS(Z) = Z.MAG
271 -- result.MAG >= 0.0
301 -- result.MAG >= 0.0
334 -- result.MAG >= 0.0
446 -- Z.MAG /= 0.0
466 -- Z.MAG /= 0.0
486 -- Z.MAG /= 0.0
525 -- Z.MAG /= 0.0
1038 -- R.MAG > 0.0
[all …]
H A Dmath_complex-body.vhdl81 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
86 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
117 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
122 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
217 return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
1359 ZOUT.MAG := L.MAG * R.MAG;
1390 ZOUT.MAG := ZL.MAG * R.MAG;
1421 ZOUT.MAG := L.MAG * ZR.MAG;
1520 ZOUT.MAG := L.MAG/R.MAG;
1558 ZOUT.MAG := L.MAG/ZR.MAG;
[all …]
/dports/cad/nvc/nvc-r1.5.3/lib/ieee/
H A Dmath_complex.vhdl167 -- result.MAG >= 0.0
212 -- ABS(Z) = Z.MAG
271 -- result.MAG >= 0.0
301 -- result.MAG >= 0.0
334 -- result.MAG >= 0.0
446 -- Z.MAG /= 0.0
466 -- Z.MAG /= 0.0
486 -- Z.MAG /= 0.0
525 -- Z.MAG /= 0.0
1038 -- R.MAG > 0.0
[all …]
H A Dmath_complex-body.vhdl81 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
86 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
117 if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
122 if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
217 return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
1359 ZOUT.MAG := L.MAG * R.MAG;
1390 ZOUT.MAG := ZL.MAG * R.MAG;
1421 ZOUT.MAG := L.MAG * ZR.MAG;
1520 ZOUT.MAG := L.MAG/R.MAG;
1558 ZOUT.MAG := L.MAG/ZR.MAG;
[all …]
/dports/cad/p5-GDS2/GDS2-3.35/
H A DTEST.dump15 MAG 1
21 MAG 1
27 MAG 1
59 MAG 0.1
69 MAG 0.1
79 MAG 0.1
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dfcopysign.f16.ll15 ; SI: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
18 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
22 ; GFX89: {{buffer|flat}}_load_ushort v[[MAG:[0-9]+]]
41 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
44 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
65 ; GCN-DAG: {{buffer|flat|global}}_load_ushort v[[MAG:[0-9]+]]
68 ; GCN-DAG: v_cvt_f32_f16_e32 v[[MAG_EXT:[0-9]+]], v[[MAG]]
90 ; GCN-DAG: {{buffer|flat|global}}_load_dword v[[MAG:[0-9]+]]
145 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
173 ; SI-DAG: v_cvt_f32_f16_e32 v[[MAG_F32:[0-9]+]], v[[MAG]]
[all …]

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