| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.c | 528 {"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
530 {"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
|
| H A D | riscv-opc.h | 323 #define MASK_FLE_D 0xfe00707f macro
932 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 325 #define MASK_FLE_D 0xfe00707f macro
986 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 349 #define MASK_FLE_D 0xfe00707f macro
1034 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 349 #define MASK_FLE_D 0xfe00707f macro
1034 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 349 #define MASK_FLE_D 0xfe00707f macro
1034 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 349 #define MASK_FLE_D 0xfe00707f macro
1034 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 631 {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
633 {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
|
| /dports/devel/gdb/gdb-11.1/opcodes/ |
| H A D | riscv-opc.c | 631 {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
633 {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
|
| /dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 631 {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
633 {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
|
| /dports/devel/binutils/binutils-2.37/opcodes/ |
| H A D | riscv-opc.c | 631 {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
633 {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | encoding.h | 615 #define MASK_FLE_D 0xfe00707f macro
2230 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | encoding.h | 617 #define MASK_FLE_D 0xfe00707f macro
3261 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|