/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
H A D | riscv-opc.h | 162 #define MATCH_DIVW 0x200403b macro 852 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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H A D | riscv-opc.c | 404 {"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
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/dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
H A D | riscv-opc.h | 162 #define MATCH_DIVW 0x200403b macro 905 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/binutils/binutils-2.37/include/opcode/ |
H A D | riscv-opc.h | 186 #define MATCH_DIVW 0x200403b macro 953 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
H A D | riscv-opc.h | 186 #define MATCH_DIVW 0x200403b macro 953 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
H A D | riscv-opc.h | 186 #define MATCH_DIVW 0x200403b macro 953 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/gdb/gdb-11.1/include/opcode/ |
H A D | riscv-opc.h | 186 #define MATCH_DIVW 0x200403b macro 953 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
H A D | encoding.h | 448 #define MATCH_DIVW 0x200403b macro 2147 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | riscv-opc.c | 501 {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | riscv-opc.c | 501 {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | riscv-opc.c | 501 {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | riscv-opc.c | 501 {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
H A D | encoding.h | 450 #define MATCH_DIVW 0x200403b macro 3178 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
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