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Searched refs:MC_SEQ_WR_CTL_D1 (Results 1 – 25 of 46) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dbtc_dpm.c1879 case MC_SEQ_WR_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2035 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
H A Dnid.h788 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dsid.h549 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcikd.h662 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dnid.h776 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dbtc_dpm.c1881 case MC_SEQ_WR_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2037 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
H A Dsid.h506 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcikd.h621 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Devergreend.h294 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dbtc_dpm.c1879 case MC_SEQ_WR_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2035 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
H A Dnid.h788 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dsid.h549 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcikd.h662 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Devergreend.h294 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/
H A Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dbtc_dpm.c1879 case MC_SEQ_WR_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2035 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
H A Dnid.h788 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dsid.h549 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
H A Dcikd.h662 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h550 #define MC_SEQ_WR_CTL_D1 0xA30 macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h550 #define MC_SEQ_WR_CTL_D1 0xA30 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h550 #define MC_SEQ_WR_CTL_D1 0xA30 macro

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