Home
last modified time | relevance | path

Searched refs:MDIV_SHIFT (Results 1 – 25 of 178) sorted by relevance

12345678

/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/imx/
H A Dclk-pll14xx.c34 #define MDIV_SHIFT 12 macro
75 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
94 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
113 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_mp_change()
124 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mpk_change()
137 old_mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_mp_change()
191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()

12345678