1package riscv 2 3// This file lists constants for CSR operations and defines methods on CSRs that 4// are implemented as compiler intrinsics. 5 6// CSR constants are used for use in CSR (Control and Status Register) compiler 7// intrinsics. 8type CSR int16 9 10// Get returns the value of the given CSR. 11func (csr CSR) Get() uintptr 12 13// Set stores a new value in the given CSR. 14func (csr CSR) Set(uintptr) 15 16// SetBits atomically sets the given bits in this ISR and returns the old value. 17func (csr CSR) SetBits(uintptr) uintptr 18 19// ClearBits atomically clears the given bits in this ISR and returns the old 20// value. 21func (csr CSR) ClearBits(uintptr) uintptr 22 23// CSR values defined in the RISC-V privileged specification. Not all values may 24// be available on any given chip. 25// 26// Source: https://github.com/riscv/riscv-isa-manual/blob/riscv-priv-1.10/src/priv-csrs.tex 27const ( 28 // User Trap Setup 29 USTATUS CSR = 0x000 // User status register. 30 UIE CSR = 0x004 // User interrupt-enable register. 31 UTVEC CSR = 0x005 // User trap handler base address. 32 33 // User Trap Handling 34 USCRATCH CSR = 0x040 // Scratch register for user trap handlers. 35 UEPC CSR = 0x041 // User exception program counter. 36 UCAUSE CSR = 0x042 // User trap cause. 37 UTVAL CSR = 0x043 // User bad address or instruction. 38 UIP CSR = 0x044 // User interrupt pending. 39 40 // User Floating-Point CSRs 41 FFLAGS CSR = 0x001 // Floating-Point Accrued Exceptions. 42 FRM CSR = 0x002 // Floating-Point Dynamic Rounding Mode. 43 FCSR CSR = 0x003 // Floating-Point Control and Status 44 45 // User Counter/Timers 46 CYCLE CSR = 0xC00 // Cycle counter for RDCYCLE instruction. 47 TIME CSR = 0xC01 // Timer for RDTIME instruction. 48 INSTRET CSR = 0xC02 // Instructions-retired counter for RDINSTRET instruction. 49 HPMCOUNTER3 CSR = 0xC03 // Performance-monitoring counter 3. 50 HPMCOUNTER4 CSR = 0xC04 // Performance-monitoring counter 4. 51 HPMCOUNTER5 CSR = 0xC05 // Performance-monitoring counter 5. 52 HPMCOUNTER6 CSR = 0xC06 // Performance-monitoring counter 6. 53 HPMCOUNTER7 CSR = 0xC07 // Performance-monitoring counter 7. 54 HPMCOUNTER8 CSR = 0xC08 // Performance-monitoring counter 8. 55 HPMCOUNTER9 CSR = 0xC09 // Performance-monitoring counter 9. 56 HPMCOUNTER10 CSR = 0xC0A // Performance-monitoring counter 10. 57 HPMCOUNTER11 CSR = 0xC0B // Performance-monitoring counter 11. 58 HPMCOUNTER12 CSR = 0xC0C // Performance-monitoring counter 12. 59 HPMCOUNTER13 CSR = 0xC0D // Performance-monitoring counter 13. 60 HPMCOUNTER14 CSR = 0xC0E // Performance-monitoring counter 14. 61 HPMCOUNTER15 CSR = 0xC0F // Performance-monitoring counter 15. 62 HPMCOUNTER16 CSR = 0xC10 // Performance-monitoring counter 16. 63 HPMCOUNTER17 CSR = 0xC11 // Performance-monitoring counter 17. 64 HPMCOUNTER18 CSR = 0xC12 // Performance-monitoring counter 18. 65 HPMCOUNTER19 CSR = 0xC13 // Performance-monitoring counter 19. 66 HPMCOUNTER20 CSR = 0xC14 // Performance-monitoring counter 20. 67 HPMCOUNTER21 CSR = 0xC15 // Performance-monitoring counter 21. 68 HPMCOUNTER22 CSR = 0xC16 // Performance-monitoring counter 22. 69 HPMCOUNTER23 CSR = 0xC17 // Performance-monitoring counter 23. 70 HPMCOUNTER24 CSR = 0xC18 // Performance-monitoring counter 24. 71 HPMCOUNTER25 CSR = 0xC19 // Performance-monitoring counter 25. 72 HPMCOUNTER26 CSR = 0xC1A // Performance-monitoring counter 26. 73 HPMCOUNTER27 CSR = 0xC1B // Performance-monitoring counter 27. 74 HPMCOUNTER28 CSR = 0xC1C // Performance-monitoring counter 28. 75 HPMCOUNTER29 CSR = 0xC1D // Performance-monitoring counter 29. 76 HPMCOUNTER30 CSR = 0xC1E // Performance-monitoring counter 30. 77 HPMCOUNTER31 CSR = 0xC1F // Performance-monitoring counter 31. 78 CYCLEH CSR = 0xC80 // Upper 32 bits of CYCLE, RV32I only. 79 TIMEH CSR = 0xC81 // Upper 32 bits of TIME, RV32I only. 80 INSTRETH CSR = 0xC82 // Upper 32 bits of INSTRET, RV32I only. 81 HPMCOUNTER3H CSR = 0xC83 // Upper 32 bits of HPMCOUNTER3, RV32I only. 82 HPMCOUNTER4H CSR = 0xC84 // Upper 32 bits of HPMCOUNTER4, RV32I only. 83 HPMCOUNTER5H CSR = 0xC85 // Upper 32 bits of HPMCOUNTER5, RV32I only. 84 HPMCOUNTER6H CSR = 0xC86 // Upper 32 bits of HPMCOUNTER6, RV32I only. 85 HPMCOUNTER7H CSR = 0xC87 // Upper 32 bits of HPMCOUNTER7, RV32I only. 86 HPMCOUNTER8H CSR = 0xC88 // Upper 32 bits of HPMCOUNTER8, RV32I only. 87 HPMCOUNTER9H CSR = 0xC89 // Upper 32 bits of HPMCOUNTER9, RV32I only. 88 HPMCOUNTER10H CSR = 0xC8A // Upper 32 bits of HPMCOUNTER10, RV32I only. 89 HPMCOUNTER11H CSR = 0xC8B // Upper 32 bits of HPMCOUNTER11, RV32I only. 90 HPMCOUNTER12H CSR = 0xC8C // Upper 32 bits of HPMCOUNTER12, RV32I only. 91 HPMCOUNTER13H CSR = 0xC8D // Upper 32 bits of HPMCOUNTER13, RV32I only. 92 HPMCOUNTER14H CSR = 0xC8E // Upper 32 bits of HPMCOUNTER14, RV32I only. 93 HPMCOUNTER15H CSR = 0xC8F // Upper 32 bits of HPMCOUNTER15, RV32I only. 94 HPMCOUNTER16H CSR = 0xC90 // Upper 32 bits of HPMCOUNTER16, RV32I only. 95 HPMCOUNTER17H CSR = 0xC91 // Upper 32 bits of HPMCOUNTER17, RV32I only. 96 HPMCOUNTER18H CSR = 0xC92 // Upper 32 bits of HPMCOUNTER18, RV32I only. 97 HPMCOUNTER19H CSR = 0xC93 // Upper 32 bits of HPMCOUNTER19, RV32I only. 98 HPMCOUNTER20H CSR = 0xC94 // Upper 32 bits of HPMCOUNTER20, RV32I only. 99 HPMCOUNTER21H CSR = 0xC95 // Upper 32 bits of HPMCOUNTER21, RV32I only. 100 HPMCOUNTER22H CSR = 0xC96 // Upper 32 bits of HPMCOUNTER22, RV32I only. 101 HPMCOUNTER23H CSR = 0xC97 // Upper 32 bits of HPMCOUNTER23, RV32I only. 102 HPMCOUNTER24H CSR = 0xC98 // Upper 32 bits of HPMCOUNTER24, RV32I only. 103 HPMCOUNTER25H CSR = 0xC99 // Upper 32 bits of HPMCOUNTER25, RV32I only. 104 HPMCOUNTER26H CSR = 0xC9A // Upper 32 bits of HPMCOUNTER26, RV32I only. 105 HPMCOUNTER27H CSR = 0xC9B // Upper 32 bits of HPMCOUNTER27, RV32I only. 106 HPMCOUNTER28H CSR = 0xC9C // Upper 32 bits of HPMCOUNTER28, RV32I only. 107 HPMCOUNTER29H CSR = 0xC9D // Upper 32 bits of HPMCOUNTER29, RV32I only. 108 HPMCOUNTER30H CSR = 0xC9E // Upper 32 bits of HPMCOUNTER30, RV32I only. 109 HPMCOUNTER31H CSR = 0xC9F // Upper 32 bits of HPMCOUNTER31, RV32I only. 110 111 // Supervisor Trap Setup 112 SSTATUS CSR = 0x100 // Supervisor status register. 113 SEDELEG CSR = 0x102 // Supervisor exception delegation register. 114 SIDELEG CSR = 0x103 // Supervisor interrupt delegation register. 115 SIE CSR = 0x104 // Supervisor interrupt-enable register. 116 STVEC CSR = 0x105 // Supervisor trap handler base address. 117 SCOUNTEREN CSR = 0x106 // Supervisor counter enable. 118 119 // Supervisor Trap Handling 120 SSCRATCH CSR = 0x140 // Scratch register for supervisor trap handlers. 121 SEPC CSR = 0x141 // Supervisor exception program counter. 122 SCAUSE CSR = 0x142 // Supervisor trap cause. 123 STVAL CSR = 0x143 // Supervisor bad address or instruction. 124 SIP CSR = 0x144 // Supervisor interrupt pending. 125 126 // Supervisor Protection and Translation 127 SATP CSR = 0x180 // Supervisor address translation and protection. 128 129 // Machine Information Registers 130 MVENDORID CSR = 0xF11 // Vendor ID. 131 MARCHID CSR = 0xF12 // Architecture ID. 132 MIMPID CSR = 0xF13 // Implementation ID. 133 MHARTID CSR = 0xF14 // Hardware thread ID. 134 135 // Machine Trap Setup 136 MSTATUS CSR = 0x300 // Machine status register. 137 MISA CSR = 0x301 // ISA and extensions 138 MEDELEG CSR = 0x302 // Machine exception delegation register. 139 MIDELEG CSR = 0x303 // Machine interrupt delegation register. 140 MIE CSR = 0x304 // Machine interrupt-enable register. 141 MTVEC CSR = 0x305 // Machine trap-handler base address. 142 MCOUNTEREN CSR = 0x306 // Machine counter enable. 143 144 // Machine Trap Handling 145 MSCRATCH CSR = 0x340 // Scratch register for machine trap handlers. 146 MEPC CSR = 0x341 // Machine exception program counter. 147 MCAUSE CSR = 0x342 // Machine trap cause. 148 MTVAL CSR = 0x343 // Machine bad address or instruction. 149 MIP CSR = 0x344 // Machine interrupt pending. 150 151 // Machine Protection and Translation 152 PMPCFG0 CSR = 0x3A0 // Physical memory protection configuration. 153 PMPCFG1 CSR = 0x3A1 // Physical memory protection configuration, RV32 only. 154 PMPCFG2 CSR = 0x3A2 // Physical memory protection configuration. 155 PMPCFG3 CSR = 0x3A3 // Physical memory protection configuration, RV32 only. 156 PMPADDR0 CSR = 0x3B0 // Physical memory protection address register 0. 157 PMPADDR1 CSR = 0x3B1 // Physical memory protection address register 1. 158 PMPADDR2 CSR = 0x3B2 // Physical memory protection address register 2. 159 PMPADDR3 CSR = 0x3B3 // Physical memory protection address register 3. 160 PMPADDR4 CSR = 0x3B4 // Physical memory protection address register 4. 161 PMPADDR5 CSR = 0x3B5 // Physical memory protection address register 5. 162 PMPADDR6 CSR = 0x3B6 // Physical memory protection address register 6. 163 PMPADDR7 CSR = 0x3B7 // Physical memory protection address register 7. 164 PMPADDR8 CSR = 0x3B8 // Physical memory protection address register 8. 165 PMPADDR9 CSR = 0x3B9 // Physical memory protection address register 9. 166 PMPADDR10 CSR = 0x3BA // Physical memory protection address register 10. 167 PMPADDR11 CSR = 0x3BB // Physical memory protection address register 11. 168 PMPADDR12 CSR = 0x3BC // Physical memory protection address register 12. 169 PMPADDR13 CSR = 0x3BD // Physical memory protection address register 13. 170 PMPADDR14 CSR = 0x3BE // Physical memory protection address register 14. 171 PMPADDR15 CSR = 0x3BF // Physical memory protection address register 15. 172 173 // Machine Counter/Timers 174 mcycle CSR = 0xB00 // Machine cycle counter. 175 minstret CSR = 0xB02 // Machine instructions-retired counter. 176 MHPMCOUNTER3 CSR = 0xB03 // Machine performance-monitoring counter 3. 177 MHPMCOUNTER4 CSR = 0xB04 // Machine performance-monitoring counter 4. 178 MHPMCOUNTER5 CSR = 0xB05 // Machine performance-monitoring counter 5. 179 MHPMCOUNTER6 CSR = 0xB06 // Machine performance-monitoring counter 6. 180 MHPMCOUNTER7 CSR = 0xB07 // Machine performance-monitoring counter 7. 181 MHPMCOUNTER8 CSR = 0xB08 // Machine performance-monitoring counter 8. 182 MHPMCOUNTER9 CSR = 0xB09 // Machine performance-monitoring counter 9. 183 MHPMCOUNTER10 CSR = 0xB0A // Machine performance-monitoring counter 10. 184 MHPMCOUNTER11 CSR = 0xB0B // Machine performance-monitoring counter 11. 185 MHPMCOUNTER12 CSR = 0xB0C // Machine performance-monitoring counter 12. 186 MHPMCOUNTER13 CSR = 0xB0D // Machine performance-monitoring counter 13. 187 MHPMCOUNTER14 CSR = 0xB0E // Machine performance-monitoring counter 14. 188 MHPMCOUNTER15 CSR = 0xB0F // Machine performance-monitoring counter 15. 189 MHPMCOUNTER16 CSR = 0xB10 // Machine performance-monitoring counter 16. 190 MHPMCOUNTER17 CSR = 0xB11 // Machine performance-monitoring counter 17. 191 MHPMCOUNTER18 CSR = 0xB12 // Machine performance-monitoring counter 18. 192 MHPMCOUNTER19 CSR = 0xB13 // Machine performance-monitoring counter 19. 193 MHPMCOUNTER20 CSR = 0xB14 // Machine performance-monitoring counter 20. 194 MHPMCOUNTER21 CSR = 0xB15 // Machine performance-monitoring counter 21. 195 MHPMCOUNTER22 CSR = 0xB16 // Machine performance-monitoring counter 22. 196 MHPMCOUNTER23 CSR = 0xB17 // Machine performance-monitoring counter 23. 197 MHPMCOUNTER24 CSR = 0xB18 // Machine performance-monitoring counter 24. 198 MHPMCOUNTER25 CSR = 0xB19 // Machine performance-monitoring counter 25. 199 MHPMCOUNTER26 CSR = 0xB1A // Machine performance-monitoring counter 26. 200 MHPMCOUNTER27 CSR = 0xB1B // Machine performance-monitoring counter 27. 201 MHPMCOUNTER28 CSR = 0xB1C // Machine performance-monitoring counter 28. 202 MHPMCOUNTER29 CSR = 0xB1D // Machine performance-monitoring counter 29. 203 MHPMCOUNTER30 CSR = 0xB1E // Machine performance-monitoring counter 30. 204 MHPMCOUNTER31 CSR = 0xB1F // Machine performance-monitoring counter 31. 205 MCYCLEH CSR = 0xB80 // Upper 32 bits of MCYCLE, RV32I only. 206 MINSTRETH CSR = 0xB82 // Upper 32 bits of MINSTRET, RV32I only. 207 MHPMCOUNTER3H CSR = 0xB83 // Upper 32 bits of MHPMCOUNTER3, RV32I only. 208 MHPMCOUNTER4H CSR = 0xB84 // Upper 32 bits of MHPMCOUNTER4, RV32I only. 209 MHPMCOUNTER5H CSR = 0xB85 // Upper 32 bits of MHPMCOUNTER5, RV32I only. 210 MHPMCOUNTER6H CSR = 0xB86 // Upper 32 bits of MHPMCOUNTER6, RV32I only. 211 MHPMCOUNTER7H CSR = 0xB87 // Upper 32 bits of MHPMCOUNTER7, RV32I only. 212 MHPMCOUNTER8H CSR = 0xB88 // Upper 32 bits of MHPMCOUNTER8, RV32I only. 213 MHPMCOUNTER9H CSR = 0xB89 // Upper 32 bits of MHPMCOUNTER9, RV32I only. 214 MHPMCOUNTER10H CSR = 0xB8A // Upper 32 bits of MHPMCOUNTER10, RV32I only. 215 MHPMCOUNTER11H CSR = 0xB8B // Upper 32 bits of MHPMCOUNTER11, RV32I only. 216 MHPMCOUNTER12H CSR = 0xB8C // Upper 32 bits of MHPMCOUNTER12, RV32I only. 217 MHPMCOUNTER13H CSR = 0xB8D // Upper 32 bits of MHPMCOUNTER13, RV32I only. 218 MHPMCOUNTER14H CSR = 0xB8E // Upper 32 bits of MHPMCOUNTER14, RV32I only. 219 MHPMCOUNTER15H CSR = 0xB8F // Upper 32 bits of MHPMCOUNTER15, RV32I only. 220 MHPMCOUNTER16H CSR = 0xB90 // Upper 32 bits of MHPMCOUNTER16, RV32I only. 221 MHPMCOUNTER17H CSR = 0xB91 // Upper 32 bits of MHPMCOUNTER17, RV32I only. 222 MHPMCOUNTER18H CSR = 0xB92 // Upper 32 bits of MHPMCOUNTER18, RV32I only. 223 MHPMCOUNTER19H CSR = 0xB93 // Upper 32 bits of MHPMCOUNTER19, RV32I only. 224 MHPMCOUNTER20H CSR = 0xB94 // Upper 32 bits of MHPMCOUNTER20, RV32I only. 225 MHPMCOUNTER21H CSR = 0xB95 // Upper 32 bits of MHPMCOUNTER21, RV32I only. 226 MHPMCOUNTER22H CSR = 0xB96 // Upper 32 bits of MHPMCOUNTER22, RV32I only. 227 MHPMCOUNTER23H CSR = 0xB97 // Upper 32 bits of MHPMCOUNTER23, RV32I only. 228 MHPMCOUNTER24H CSR = 0xB98 // Upper 32 bits of MHPMCOUNTER24, RV32I only. 229 MHPMCOUNTER25H CSR = 0xB99 // Upper 32 bits of MHPMCOUNTER25, RV32I only. 230 MHPMCOUNTER26H CSR = 0xB9A // Upper 32 bits of MHPMCOUNTER26, RV32I only. 231 MHPMCOUNTER27H CSR = 0xB9B // Upper 32 bits of MHPMCOUNTER27, RV32I only. 232 MHPMCOUNTER28H CSR = 0xB9C // Upper 32 bits of MHPMCOUNTER28, RV32I only. 233 MHPMCOUNTER29H CSR = 0xB9D // Upper 32 bits of MHPMCOUNTER29, RV32I only. 234 MHPMCOUNTER30H CSR = 0xB9E // Upper 32 bits of MHPMCOUNTER30, RV32I only. 235 MHPMCOUNTER31H CSR = 0xB9F // Upper 32 bits of MHPMCOUNTER31, RV32I only. 236 237 // Machine Counter Setup 238 MHPMEVENT4 CSR = 0x324 // Machine performance-monitoring event selector 4. 239 MHPMEVENT5 CSR = 0x325 // Machine performance-monitoring event selector 5. 240 MHPMEVENT6 CSR = 0x326 // Machine performance-monitoring event selector 6. 241 MHPMEVENT7 CSR = 0x327 // Machine performance-monitoring event selector 7. 242 MHPMEVENT8 CSR = 0x328 // Machine performance-monitoring event selector 8. 243 MHPMEVENT9 CSR = 0x329 // Machine performance-monitoring event selector 9. 244 MHPMEVENT10 CSR = 0x32A // Machine performance-monitoring event selector 10. 245 MHPMEVENT11 CSR = 0x32B // Machine performance-monitoring event selector 11. 246 MHPMEVENT12 CSR = 0x32C // Machine performance-monitoring event selector 12. 247 MHPMEVENT13 CSR = 0x32D // Machine performance-monitoring event selector 13. 248 MHPMEVENT14 CSR = 0x32E // Machine performance-monitoring event selector 14. 249 MHPMEVENT15 CSR = 0x32F // Machine performance-monitoring event selector 15. 250 MHPMEVENT16 CSR = 0x330 // Machine performance-monitoring event selector 16. 251 MHPMEVENT17 CSR = 0x331 // Machine performance-monitoring event selector 17. 252 MHPMEVENT18 CSR = 0x332 // Machine performance-monitoring event selector 18. 253 MHPMEVENT19 CSR = 0x333 // Machine performance-monitoring event selector 19. 254 MHPMEVENT20 CSR = 0x334 // Machine performance-monitoring event selector 20. 255 MHPMEVENT21 CSR = 0x335 // Machine performance-monitoring event selector 21. 256 MHPMEVENT22 CSR = 0x336 // Machine performance-monitoring event selector 22. 257 MHPMEVENT23 CSR = 0x337 // Machine performance-monitoring event selector 23. 258 MHPMEVENT24 CSR = 0x338 // Machine performance-monitoring event selector 24. 259 MHPMEVENT25 CSR = 0x339 // Machine performance-monitoring event selector 25. 260 MHPMEVENT26 CSR = 0x33A // Machine performance-monitoring event selector 26. 261 MHPMEVENT27 CSR = 0x33B // Machine performance-monitoring event selector 27. 262 MHPMEVENT28 CSR = 0x33C // Machine performance-monitoring event selector 28. 263 MHPMEVENT29 CSR = 0x33D // Machine performance-monitoring event selector 29. 264 MHPMEVENT30 CSR = 0x33E // Machine performance-monitoring event selector 30. 265 MHPMEVENT31 CSR = 0x33F // Machine performance-monitoring event selector 31. 266 267 // Debug/Trace Registers (shared with Debug Mode) 268 TSELECT CSR = 0x7A0 // Debug/Trace trigger register select. 269 TDATA1 CSR = 0x7A1 // First Debug/Trace trigger data register. 270 TDATA2 CSR = 0x7A2 // Second Debug/Trace trigger data register. 271 TDATA3 CSR = 0x7A3 // Third Debug/Trace trigger data register. 272 273 // Debug Mode Registers 274 DCSR CSR = 0x7B0 // Debug control and status register. 275 DPC CSR = 0x7B1 // Debug PC. 276 DSCRATCH CSR = 0x7B2 // Debug scratch register. 277) 278