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Searched refs:MII_TG3_AUXCTL_SHDWSEL_MISC (Results 1 – 22 of 22) sorted by relevance

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2358 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/tg3/
H A Dtg3_phy.c425 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
554 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
591 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
598 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
612 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
614 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
H A Dtg3.h2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h2341 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
H A Dtg3.c1307 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
1316 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
2277 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
2284 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
2297 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2299 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h2341 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
H A Dtg3.c1307 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
1316 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
2277 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
2284 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
2297 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2299 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/broadcom/
H A Dtg3.h2341 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 macro
H A Dtg3.c1307 MII_TG3_AUXCTL_SHDWSEL_MISC); in tg3_phy_auxctl_read()
1316 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) in tg3_phy_auxctl_write()
2277 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy); in tg3_phy_toggle_automdix()
2284 MII_TG3_AUXCTL_SHDWSEL_MISC, phy); in tg3_phy_toggle_automdix()
2297 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2299 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()