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Searched refs:MIPS16OP_MASK_REGR32 (Results 1 – 25 of 35) sorted by relevance

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/dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/opcode/
H A Dmips.h714 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/include/opcode/
H A Dmips.h803 #define MIPS16OP_MASK_REGR32 0x1f
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/include/opcode/
H A Dmips.h814 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/include/opcode/
H A Dmips.h803 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/include/opcode/
H A Dmips.h948 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/djgpp-binutils/binutils-2.17/include/opcode/
H A Dmips.h874 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/avr-gdb/gdb-7.3.1/include/opcode/
H A Dmips.h1030 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/gdb761/gdb-7.6.1/include/opcode/
H A Dmips.h1310 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/include/opcode/
H A Dmips.h1645 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/binutils/binutils-2.37/include/opcode/
H A Dmips.h1852 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/include/opcode/
H A Dmips.h1772 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/
H A Dmips.h1852 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/gnulibiberty/binutils-2.37/include/opcode/
H A Dmips.h1852 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/lang/gnatdroid-binutils/binutils-2.27/include/opcode/
H A Dmips.h1772 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/devel/gdb/gdb-11.1/include/opcode/
H A Dmips.h1852 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/
H A Dmips.h1809 #define MIPS16OP_MASK_REGR32 0x1f macro
/dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/
H A Dmips-dis.c874 & MIPS16OP_MASK_REGR32)]);
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dmips-dis.c1458 & MIPS16OP_MASK_REGR32)]);
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-dis.c1442 & MIPS16OP_MASK_REGR32)]);
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-dis.c1442 & MIPS16OP_MASK_REGR32)]);
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/
H A Dmips-dis.c1437 & MIPS16OP_MASK_REGR32)]); in print_mips16_insn_arg()
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dmips-dis.c1328 & MIPS16OP_MASK_REGR32)]); in print_mips16_insn_arg()
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dmips-dis.c1547 & MIPS16OP_MASK_REGR32)]); in print_mips16_insn_arg()
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dmips-dis.c942 #define MIPS16OP_MASK_REGR32 0x1f macro
4352 & MIPS16OP_MASK_REGR32)]);
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dmips.c990 #define MIPS16OP_MASK_REGR32 0x1f macro
5320 & MIPS16OP_MASK_REGR32)]);

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