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Searched refs:MMC_TIMING_UHS_SDR104 (Results 1 – 25 of 283) sorted by relevance

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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/mmc/
H A Dzynq_sdhci.c68 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
220 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sdcardclk_set_phase()
276 case MMC_TIMING_UHS_SDR104: in sdhci_zynqmp_sampleclk_set_phase()
331 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sdcardclk_set_phase()
395 case MMC_TIMING_UHS_SDR104: in sdhci_versal_sampleclk_set_phase()
490 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90; in arasan_dt_parse_clk_phases()
515 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104, in arasan_dt_parse_clk_phases()

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