Home
last modified time | relevance | path

Searched refs:MMDC_MPDGCTRL1 (Results 1 – 25 of 74) sorted by relevance

123

/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/freescale/s32v234evb/
H A Dlpddr2.c115 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
126 mmdc_addr + MMDC_MPDGCTRL1); in config_mmdc()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h53 #define MMDC_MPDGCTRL1 0x840 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h403 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-mx7ulp/
H A Dimx-regs.h423 #define MMDC_MPDGCTRL1 ((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET)) macro

123