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Searched refs:MSA (Results 1 – 25 of 3513) sorted by relevance

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/dports/math/maxima/maxima-5.43.2/interfaces/emacs/imaxima/breqn097a/
H A Dmsabm.sym35 \DeclareFlexSymbol{\boxdot} {Bin}{MSA}{00}
36 \DeclareFlexSymbol{\boxplus} {Bin}{MSA}{01}
37 \DeclareFlexSymbol{\boxtimes} {Bin}{MSA}{02}
38 \DeclareFlexSymbol{\square} {Ord}{MSA}{03}
39 \DeclareFlexSymbol{\blacksquare} {Ord}{MSA}{04}
40 \DeclareFlexSymbol{\centerdot} {Bin}{MSA}{05}
41 \DeclareFlexSymbol{\lozenge} {Ord}{MSA}{06}
42 \DeclareFlexSymbol{\blacklozenge} {Ord}{MSA}{07}
47 \DeclareFlexSymbol{\boxminus} {Bin}{MSA}{0C}
48 \DeclareFlexSymbol{\Vdash} {Rel}{MSA}{0D}
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
279 #define MSA ASE_MSA macro
1687 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1728 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1729 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1730 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1731 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1846 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
281 #define MSA ASE_MSA macro
1710 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1751 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1752 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1753 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1754 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1869 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
279 #define MSA ASE_MSA macro
1687 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1728 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1729 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1730 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1731 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1846 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
281 #define MSA ASE_MSA macro
1710 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1751 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1752 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1753 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1754 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1869 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
281 #define MSA ASE_MSA macro
1710 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1751 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1752 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1753 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1754 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1869 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A Dmicromips-opc.c116 case 'd': REG (5, 6, MSA); in decode_micromips_operand()
117 case 'e': REG (5, 11, MSA); in decode_micromips_operand()
118 case 'h': REG (5, 16, MSA); in decode_micromips_operand()
281 #define MSA ASE_MSA macro
1710 {"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 },
1751 {"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1752 {"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1753 {"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1754 {"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 },
1869 {"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
[all …]
/dports/biology/clustal-omega/clustal-omega-1.2.4/src/squid/
H A Dmsa.h177 } MSA; typedef
230 extern void MSAFree(MSA *msa);
243 extern void MSAExpand(MSA *msa);
253 extern void MSAVerifyParse(MSA *msa);
259 extern void MSAMingap(MSA *msa);
260 extern void MSANogap(MSA *msa);
262 extern void MSASmallerAlignment(MSA *msa, int *useme, MSA **ret_new);
273 extern MSA *ReadA2M(MSAFILE *afp);
295 extern MSA *ReadMSF(MSAFILE *afp);
300 extern MSA *ReadPhylip(MSAFILE *afp);
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/msa/
H A Dimmediates.ll14 ; MSA-LABEL: addvi_b:
18 ; MSA-NEXT: jr $ra
36 ; MSA-LABEL: andi_b:
40 ; MSA-NEXT: jr $ra
58 ; MSA-LABEL: bclri_b:
62 ; MSA-NEXT: jr $ra
85 ; MSA-NEXT: jr $ra
111 ; MSA-NEXT: jr $ra
158 ; MSA-LABEL: bmzi_b:
338 ; MSA-LABEL: ldi_b:
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dimmediates.ll14 ; MSA-LABEL: addvi_b:
18 ; MSA-NEXT: jr $ra
36 ; MSA-LABEL: andi_b:
40 ; MSA-NEXT: jr $ra
58 ; MSA-LABEL: bclri_b:
62 ; MSA-NEXT: jr $ra
85 ; MSA-NEXT: jr $ra
111 ; MSA-NEXT: jr $ra
158 ; MSA-LABEL: bmzi_b:
338 ; MSA-LABEL: ldi_b:
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dimmediates.ll14 ; MSA-LABEL: addvi_b:
18 ; MSA-NEXT: jr $ra
36 ; MSA-LABEL: andi_b:
40 ; MSA-NEXT: jr $ra
58 ; MSA-LABEL: bclri_b:
62 ; MSA-NEXT: jr $ra
85 ; MSA-NEXT: jr $ra
111 ; MSA-NEXT: jr $ra
158 ; MSA-LABEL: bmzi_b:
338 ; MSA-LABEL: ldi_b:
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/
H A Dimmediates.ll14 ; MSA-LABEL: addvi_b:
18 ; MSA-NEXT: jr $ra
36 ; MSA-LABEL: andi_b:
40 ; MSA-NEXT: jr $ra
58 ; MSA-LABEL: bclri_b:
62 ; MSA-NEXT: jr $ra
85 ; MSA-NEXT: jr $ra
111 ; MSA-NEXT: jr $ra
158 ; MSA-LABEL: bmzi_b:
338 ; MSA-LABEL: ldi_b:
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/msa/
H A Dimmediates.ll14 ; MSA-LABEL: addvi_b:
18 ; MSA-NEXT: jr $ra
36 ; MSA-LABEL: andi_b:
40 ; MSA-NEXT: jr $ra
58 ; MSA-LABEL: bclri_b:
62 ; MSA-NEXT: jr $ra
85 ; MSA-NEXT: jr $ra
111 ; MSA-NEXT: jr $ra
158 ; MSA-LABEL: bmzi_b:
338 ; MSA-LABEL: ldi_b:
[all …]
/dports/biology/ugene/ugene-40.1/src/plugins_3rdparty/umuscle/src/muscle/
H A Dobjscore.h4 SCORE ScoreSeqPairGaps(const MSA &msa1, unsigned uSeqIndex1,
5 const MSA &msa2, unsigned uSeqIndex2);
6 SCORE ScoreSeqPairLetters(const MSA &msa1, unsigned uSeqIndex1,
7 const MSA &msa2, unsigned uSeqIndex2);
10 SCORE ObjScore(const MSA &msa, const unsigned SeqIndexes1[],
13 SCORE ObjScoreIds(const MSA &msa, const unsigned Ids1[],
18 SCORE ObjScoreDP(const MSA &msa1, const MSA &msa2, SCORE MatchScore[] = 0);
19 SCORE ObjScorePS(const MSA &msa, SCORE MatchScore[] = 0);
20 SCORE ObjScoreSP(const MSA &msa, SCORE MatchScore[] = 0);
21 SCORE ObjScoreXP(const MSA &msa, const MSA &msa2);
[all …]
H A Dmsa.h13 class MSA
16 MSA();
17 virtual ~MSA();
122 static bool SeqsEq(const MSA &a1, unsigned uSeqIndex1, const MSA &a2,
172 MSA &msaOut);
173 void MSACat(const MSA &msa1, const MSA &msa2, MSA &msaCat);
174 void MSAAppend(MSA &msa1, const MSA &msa2);
176 MSA &msaOut);
177 void AssertMSAEq(const MSA &msa1, const MSA &msa2);
178 void AssertMSAEqIgnoreCaseAndGaps(const MSA &msa1, const MSA &msa2);
[all …]
/dports/biology/muscle/muscle-3.8.1551/
H A Dobjscore.h4 SCORE ScoreSeqPairGaps(const MSA &msa1, unsigned uSeqIndex1,
5 const MSA &msa2, unsigned uSeqIndex2);
6 SCORE ScoreSeqPairLetters(const MSA &msa1, unsigned uSeqIndex1,
7 const MSA &msa2, unsigned uSeqIndex2);
10 SCORE ObjScore(const MSA &msa, const unsigned SeqIndexes1[],
13 SCORE ObjScoreIds(const MSA &msa, const unsigned Ids1[],
18 SCORE ObjScoreDP(const MSA &msa1, const MSA &msa2, SCORE MatchScore[] = 0);
19 SCORE ObjScorePS(const MSA &msa, SCORE MatchScore[] = 0);
20 SCORE ObjScoreSP(const MSA &msa, SCORE MatchScore[] = 0);
21 SCORE ObjScoreXP(const MSA &msa, const MSA &msa2);
[all …]
H A Dmsa.h12 class MSA
15 MSA();
16 virtual ~MSA();
117 static bool SeqsEq(const MSA &a1, unsigned uSeqIndex1, const MSA &a2,
166 MSA &msaOut);
167 void MSACat(const MSA &msa1, const MSA &msa2, MSA &msaCat);
168 void MSAAppend(MSA &msa1, const MSA &msa2);
170 MSA &msaOut);
171 void AssertMSAEq(const MSA &msa1, const MSA &msa2);
172 void AssertMSAEqIgnoreCaseAndGaps(const MSA &msa1, const MSA &msa2);
[all …]
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1414 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1415 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1416 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1417 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1418 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1419 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1420 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1421 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1422 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1414 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1415 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1416 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1417 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1418 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1419 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1420 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1421 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1422 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1414 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1415 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1416 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1417 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1418 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1419 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1420 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1421 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1422 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dmips.c1239 #define MSA INSN_MSA
1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dmips.c1239 #define MSA INSN_MSA macro
1424 {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1425 {"sll.h", "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1426 {"sll.w", "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1427 {"sll.d", "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1428 {"slli.b", "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS, 0, MSA},
1429 {"slli.h", "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS, 0, MSA},
1430 {"slli.w", "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS, 0, MSA},
1431 {"slli.d", "+d,+e,'", 0x78000009, 0xffc0003f, WR_VD|RD_VS, 0, MSA},
1432 {"sra.b", "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
[all …]

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