| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) macro
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/marvell/mvpp2/ |
| H A D | mvpp2.h | 39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 632 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4921 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 632 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4921 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 632 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4921 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/net/ |
| H A D | mvpp2.c | 632 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4921 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/net/ |
| H A D | mvpp2.c | 624 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2)) macro
4987 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val); in mvpp2_tx_fifo_init()
|