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Searched refs:MXC_CSPICTRL_TC (Results 1 – 25 of 111) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/spi/
H A Dmxc_spi.c59 #define MXC_CSPICTRL_TC (1 << 8) macro
96 #define MXC_CSPICTRL_TC (1 << 7) macro
251 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg()
276 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
286 while ((reg_read(mxcs->base + MXC_CSPISTAT) & MXC_CSPICTRL_TC) == 0) in spi_xchg_single()
291 MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/spi/
H A Dmxc_spi.c54 #define MXC_CSPICTRL_TC BIT(7) macro
59 #define MXC_CSPICTRL_TC BIT(8) macro
86 #define MXC_CSPICTRL_TC BIT(7) macro
314 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_cfg_mxc()
342 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()
391 while ((status & MXC_CSPICTRL_TC) == 0) { in spi_xchg_single()
400 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); in spi_xchg_single()

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