/dports/multimedia/libv4l/linux-5.13-rc2/arch/arc/plat-hsdk/ |
H A D | platform.c | 126 M_HS_RTT, enumerator 239 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in hsdk_init_memory_bridge() 240 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in hsdk_init_memory_bridge() 241 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in hsdk_init_memory_bridge() 242 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in hsdk_init_memory_bridge() 243 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in hsdk_init_memory_bridge()
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arc/plat-hsdk/ |
H A D | platform.c | 126 M_HS_RTT, enumerator 239 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in hsdk_init_memory_bridge() 240 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in hsdk_init_memory_bridge() 241 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in hsdk_init_memory_bridge() 242 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in hsdk_init_memory_bridge() 243 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in hsdk_init_memory_bridge()
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arc/plat-hsdk/ |
H A D | platform.c | 126 M_HS_RTT, enumerator 239 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in hsdk_init_memory_bridge() 240 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in hsdk_init_memory_bridge() 241 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in hsdk_init_memory_bridge() 242 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in hsdk_init_memory_bridge() 243 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in hsdk_init_memory_bridge()
|
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/synopsys/hsdk/ |
H A D | hsdk.c | 426 M_HS_RTT, enumerator 489 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 490 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 491 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 492 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 493 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/synopsys/hsdk/ |
H A D | hsdk.c | 426 M_HS_RTT, enumerator 489 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 490 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 491 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 492 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 493 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/synopsys/hsdk/ |
H A D | hsdk.c | 426 M_HS_RTT, enumerator 489 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 490 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 491 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 492 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 493 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/synopsys/hsdk/ |
H A D | hsdk.c | 426 M_HS_RTT, enumerator 489 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 490 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 491 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 492 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 493 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/synopsys/hsdk/ |
H A D | hsdk.c | 426 M_HS_RTT, enumerator 489 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 490 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 491 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 492 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 493 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-chip/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/synopsys/hsdk/ |
H A D | hsdk.c | 554 M_HS_RTT, enumerator 617 writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT)); in init_memory_bridge() 618 writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT)); in init_memory_bridge() 619 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT)); in init_memory_bridge() 620 writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT)); in init_memory_bridge() 621 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT)); in init_memory_bridge()
|