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Searched refs:M_REG_NUM_BANKS (Results 1 – 25 of 38) sorted by relevance

12

/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h59 uint32_t prigroup[M_REG_NUM_BANKS];
90 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/
H A Darmv7m_nvic.h59 uint32_t prigroup[M_REG_NUM_BANKS];
90 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/
H A Darmv7m_nvic.h61 uint32_t prigroup[M_REG_NUM_BANKS];
92 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h59 uint32_t prigroup[M_REG_NUM_BANKS];
90 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/
H A Darmv7m_nvic.h59 uint32_t prigroup[M_REG_NUM_BANKS];
90 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/intc/
H A Darmv7m_nvic.h59 uint32_t prigroup[M_REG_NUM_BANKS];
90 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Darmv7m_nvic.h61 uint32_t prigroup[M_REG_NUM_BANKS];
94 SysTickState systick[M_REG_NUM_BANKS];
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h86 M_REG_NUM_BANKS = 2, enumerator
495 uint32_t vecbase[M_REG_NUM_BANKS];
512 uint32_t csselr[M_REG_NUM_BANKS];
513 uint32_t scr[M_REG_NUM_BANKS];
514 uint32_t msplim[M_REG_NUM_BANKS];
515 uint32_t psplim[M_REG_NUM_BANKS];
621 uint32_t rnr[M_REG_NUM_BANKS];
631 uint32_t *rbar[M_REG_NUM_BANKS];
632 uint32_t *rlar[M_REG_NUM_BANKS];
633 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h78 M_REG_NUM_BANKS = 2, enumerator
528 uint32_t csselr[M_REG_NUM_BANKS];
529 uint32_t scr[M_REG_NUM_BANKS];
532 uint32_t fpcar[M_REG_NUM_BANKS];
533 uint32_t fpccr[M_REG_NUM_BANKS];
535 uint32_t cpacr[M_REG_NUM_BANKS];
662 uint32_t rnr[M_REG_NUM_BANKS];
672 uint32_t *rbar[M_REG_NUM_BANKS];
673 uint32_t *rlar[M_REG_NUM_BANKS];
674 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c257 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
299 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
311 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h78 M_REG_NUM_BANKS = 2, enumerator
528 uint32_t csselr[M_REG_NUM_BANKS];
529 uint32_t scr[M_REG_NUM_BANKS];
532 uint32_t fpcar[M_REG_NUM_BANKS];
533 uint32_t fpccr[M_REG_NUM_BANKS];
535 uint32_t cpacr[M_REG_NUM_BANKS];
662 uint32_t rnr[M_REG_NUM_BANKS];
672 uint32_t *rbar[M_REG_NUM_BANKS];
673 uint32_t *rlar[M_REG_NUM_BANKS];
674 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c257 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
299 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
311 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dcpu.h83 M_REG_NUM_BANKS = 2, enumerator
543 uint32_t csselr[M_REG_NUM_BANKS];
544 uint32_t scr[M_REG_NUM_BANKS];
547 uint32_t fpcar[M_REG_NUM_BANKS];
548 uint32_t fpccr[M_REG_NUM_BANKS];
550 uint32_t cpacr[M_REG_NUM_BANKS];
687 uint32_t rnr[M_REG_NUM_BANKS];
697 uint32_t *rbar[M_REG_NUM_BANKS];
698 uint32_t *rlar[M_REG_NUM_BANKS];
699 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dcpu.h78 M_REG_NUM_BANKS = 2, enumerator
535 uint32_t csselr[M_REG_NUM_BANKS];
536 uint32_t scr[M_REG_NUM_BANKS];
539 uint32_t fpcar[M_REG_NUM_BANKS];
540 uint32_t fpccr[M_REG_NUM_BANKS];
542 uint32_t cpacr[M_REG_NUM_BANKS];
669 uint32_t rnr[M_REG_NUM_BANKS];
679 uint32_t *rbar[M_REG_NUM_BANKS];
680 uint32_t *rlar[M_REG_NUM_BANKS];
681 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dcpu.h78 M_REG_NUM_BANKS = 2, enumerator
535 uint32_t csselr[M_REG_NUM_BANKS];
536 uint32_t scr[M_REG_NUM_BANKS];
539 uint32_t fpcar[M_REG_NUM_BANKS];
540 uint32_t fpccr[M_REG_NUM_BANKS];
542 uint32_t cpacr[M_REG_NUM_BANKS];
669 uint32_t rnr[M_REG_NUM_BANKS];
679 uint32_t *rbar[M_REG_NUM_BANKS];
680 uint32_t *rlar[M_REG_NUM_BANKS];
681 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dcpu.h83 M_REG_NUM_BANKS = 2, enumerator
552 uint32_t csselr[M_REG_NUM_BANKS];
553 uint32_t scr[M_REG_NUM_BANKS];
556 uint32_t fpcar[M_REG_NUM_BANKS];
557 uint32_t fpccr[M_REG_NUM_BANKS];
559 uint32_t cpacr[M_REG_NUM_BANKS];
696 uint32_t rnr[M_REG_NUM_BANKS];
706 uint32_t *rbar[M_REG_NUM_BANKS];
707 uint32_t *rlar[M_REG_NUM_BANKS];
708 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dcpu.h84 M_REG_NUM_BANKS = 2, enumerator
558 uint32_t csselr[M_REG_NUM_BANKS];
559 uint32_t scr[M_REG_NUM_BANKS];
562 uint32_t fpcar[M_REG_NUM_BANKS];
563 uint32_t fpccr[M_REG_NUM_BANKS];
565 uint32_t cpacr[M_REG_NUM_BANKS];
703 uint32_t rnr[M_REG_NUM_BANKS];
713 uint32_t *rbar[M_REG_NUM_BANKS];
714 uint32_t *rlar[M_REG_NUM_BANKS];
715 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dcpu.h84 M_REG_NUM_BANKS = 2, enumerator
558 uint32_t csselr[M_REG_NUM_BANKS];
559 uint32_t scr[M_REG_NUM_BANKS];
562 uint32_t fpcar[M_REG_NUM_BANKS];
563 uint32_t fpccr[M_REG_NUM_BANKS];
565 uint32_t cpacr[M_REG_NUM_BANKS];
703 uint32_t rnr[M_REG_NUM_BANKS];
713 uint32_t *rbar[M_REG_NUM_BANKS];
714 uint32_t *rlar[M_REG_NUM_BANKS];
715 uint32_t mair0[M_REG_NUM_BANKS];
[all …]
H A Dmachine.c258 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
300 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
301 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
312 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
314 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS),
315 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS),
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Darmv7m_nvic.h61 uint32_t prigroup[M_REG_NUM_BANKS];

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