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Searched refs:MachineRegisterInfo (Results 1 – 25 of 4173) sorted by relevance

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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
118 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
116 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
H A DAMDGPURegisterBankInfo.h53 MachineRegisterInfo &MRI,
60 MachineRegisterInfo &MRI) const;
64 MachineRegisterInfo &MRI,
67 MachineRegisterInfo &MRI,
74 MachineRegisterInfo &MRI) const;
77 MachineRegisterInfo &MRI) const;
81 MachineRegisterInfo &MRI, int RSrcIdx) const;
143 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
149 unsigned getMappingType(const MachineRegisterInfo &MRI,
184 MachineRegisterInfo &MRI,
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h38 MachineRegisterInfo &MRI,
43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
63 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
74 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
83 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
118 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h38 MachineRegisterInfo &MRI,
43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
70 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
74 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
83 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
123 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h38 MachineRegisterInfo &MRI,
43 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
70 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
74 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
83 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
123 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
122 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h42 MachineRegisterInfo &MRI,
47 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
67 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
78 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
87 bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
122 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h38 class MachineRegisterInfo; variable
88 Register constrainRegToClass(MachineRegisterInfo &MRI,
103 MachineRegisterInfo &MRI,
122 MachineRegisterInfo &MRI,
192 Register VReg, const MachineRegisterInfo &MRI,
214 const MachineRegisterInfo &MRI);
250 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef()
279 ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI);
375 const MachineRegisterInfo &MRI,
381 const MachineRegisterInfo &MRI,
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h33 class MachineRegisterInfo; variable
48 Register constrainRegToClass(MachineRegisterInfo &MRI,
63 MachineRegisterInfo &MRI,
82 MachineRegisterInfo &MRI,
129 const MachineRegisterInfo &MRI);
163 const MachineRegisterInfo &MRI);
187 const MachineRegisterInfo &MRI);
198 const MachineRegisterInfo &MRI);
211 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
266 const MachineRegisterInfo &MRI);
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h33 class MachineRegisterInfo; variable
48 Register constrainRegToClass(MachineRegisterInfo &MRI,
63 MachineRegisterInfo &MRI,
82 MachineRegisterInfo &MRI,
129 const MachineRegisterInfo &MRI);
163 const MachineRegisterInfo &MRI);
187 const MachineRegisterInfo &MRI);
198 const MachineRegisterInfo &MRI);
211 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
266 const MachineRegisterInfo &MRI);
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h35 class MachineRegisterInfo; variable
85 Register constrainRegToClass(MachineRegisterInfo &MRI,
100 MachineRegisterInfo &MRI,
119 MachineRegisterInfo &MRI,
166 const MachineRegisterInfo &MRI);
202 const MachineRegisterInfo &MRI);
238 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef()
252 const MachineRegisterInfo &MRI);
272 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
352 const MachineRegisterInfo &MRI);
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/include/llvm/CodeGen/GlobalISel/
H A DUtils.h35 class MachineRegisterInfo; variable
85 Register constrainRegToClass(MachineRegisterInfo &MRI,
100 MachineRegisterInfo &MRI,
119 MachineRegisterInfo &MRI,
166 const MachineRegisterInfo &MRI);
202 const MachineRegisterInfo &MRI);
238 T *getOpcodeDef(Register Reg, const MachineRegisterInfo &MRI) { in getOpcodeDef()
252 const MachineRegisterInfo &MRI);
272 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
352 const MachineRegisterInfo &MRI);
[all …]

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