| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 458 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
459 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
460 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 456 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
457 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
458 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 458 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
459 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
460 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 456 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
457 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
458 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 458 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
459 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
460 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 456 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
457 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
458 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 460 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
461 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
462 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | ARMRegisterBankInfo.cpp | 455 const MachineOperand &MaybeReg = MI.getOperand(0); in getInstrMapping() local
456 if (MaybeReg.isReg() && MaybeReg.getReg()) { in getInstrMapping()
457 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits(); in getInstrMapping()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 27776 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredRetpoline() local
27777 if (MaybeReg) { in EmitLoweredRetpoline()
27778 AvailableReg = MaybeReg; in EmitLoweredRetpoline()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 28977 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredRetpoline() local
28978 if (MaybeReg) { in EmitLoweredRetpoline()
28979 AvailableReg = MaybeReg; in EmitLoweredRetpoline()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30055 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredRetpoline() local
30056 if (MaybeReg) { in EmitLoweredRetpoline()
30057 AvailableReg = MaybeReg; in EmitLoweredRetpoline()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31460 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
31461 if (MaybeReg) { in EmitLoweredIndirectThunk()
31462 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31448 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredRetpoline() local
31449 if (MaybeReg) { in EmitLoweredRetpoline()
31450 AvailableReg = MaybeReg; in EmitLoweredRetpoline()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31460 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
31461 if (MaybeReg) { in EmitLoweredIndirectThunk()
31462 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 32748 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
32749 if (MaybeReg) { in EmitLoweredIndirectThunk()
32750 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 33453 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
33454 if (MaybeReg) { in EmitLoweredIndirectThunk()
33455 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 32282 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
32283 if (MaybeReg) { in EmitLoweredIndirectThunk()
32284 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 33453 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredIndirectThunk() local
33454 if (MaybeReg) { in EmitLoweredIndirectThunk()
33455 AvailableReg = MaybeReg; in EmitLoweredIndirectThunk()
|