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Searched refs:N54 (Results 1 – 25 of 201) sorted by relevance

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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A D	mips-opc.c	110 #define N54 INSN_5400 macro 166 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, N54 }, 168 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, N54 }, 297 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 299 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 362 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 911 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N54 }, 914 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N54 }, 917 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N54 }, 1170 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N54 }, [all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A D	mips-opc.c	110 #define N54 INSN_5400 macro 166 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 168 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 293 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 295 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 358 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 903 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 906 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 909 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 1162 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A D	mips-opc.c	110 #define N54 INSN_5400 macro 166 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, N54 }, 168 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, N54 }, 297 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 299 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 362 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, N54 }, 911 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N54 }, 914 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N54 }, 917 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N54 }, 1170 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N54 }, [all …]
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A D	mips-opc.c	110 #define N54 INSN_5400 macro 196 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 198 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 320 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 322 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 385 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 985 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 988 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 991 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 1244 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/
H A D	mips-opc.c	122 #define N54 INSN_5400 macro 214 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 216 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D\|RD_S\|RD_T, 0, N54 }, 342 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 344 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 417 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1078 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 1081 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 1084 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 1359 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A D	mips-opc.c	121 #define N54 INSN_5400 macro 415 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 417 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 490 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 492 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 509 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1178 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 1181 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 1184 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 1479 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A D	mips-opc.c	125 #define N54 INSN_5400 macro 443 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 445 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 519 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 521 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 539 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1357 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 1360 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 1363 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 1669 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A D	mips-dis.c	1141 #define N54 INSN_5400 macro 1350 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1352 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1415 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1417 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 1432 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2030 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2033 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2036 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 2289 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu/qemu-6.2.0/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2093 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2095 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2158 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2160 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2175 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2779 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2782 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2785 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3040 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2093 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2095 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2158 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2160 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2175 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2779 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2782 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2785 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3040 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2093 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2095 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2158 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2160 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2175 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2779 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2782 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2785 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3040 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A D	mips.c	1194 #define N54 INSN_5400 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A D	mips.c	1194 #define N54 INSN_5400 macro 2103 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2105 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2168 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2170 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2185 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2789 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 2792 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 2795 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3050 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A D	mips.c	1205 #define N54 INSN_5400 macro 2324 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2326 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2389 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2391 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 2406 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC\|RD_S\|RD_T, 0, N54 }, 3012 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 }, 3015 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 }, 3018 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 }, 3273 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 }, [all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A D	mips-opc.c	324 #define N54 INSN_5400 macro 676 {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 705 {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 815 {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, N54, 0, 0 }, 1387 {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1660 {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1764 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1767 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1770 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 2083 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1\|FP_D, WR_MACC, N54, 0, 0 }, [all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A D	mips-opc.c	324 #define N54 INSN_5400 macro 676 {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 705 {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 815 {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, N54, 0, 0 }, 1387 {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1660 {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1764 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1767 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1770 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 2083 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1\|FP_D, WR_MACC, N54, 0, 0 }, [all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A D	mips-opc.c	324 #define N54 INSN_5400 macro 676 {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 705 {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 815 {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, N54, 0, 0 }, 1387 {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1660 {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1764 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1767 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1770 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 2083 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1\|FP_D, WR_MACC, N54, 0, 0 }, [all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A D	mips-opc.c	324 #define N54 INSN_5400 macro 676 {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 705 {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 815 {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1\|RD_2\|WR_CC\|FP_D, 0, N54, 0, 0 }, 1387 {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1660 {"or.ob", "D,S,Q", 0x4800000e, 0xfc20003f, WR_1\|RD_2\|RD_3\|FP_D, 0, N54, 0, 0 }, 1764 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1767 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 1770 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_1\|FP_D, RD_MACC, N54, 0, 0 }, 2083 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_1\|FP_D, WR_MACC, N54, 0, 0 }, [all …]
/dports/science/openbabel/openbabel-3.1.1/test/pdb_ligands_sdf/rdkit_addh/
H A D	5lgr_qvr.sdf	`108 N54`
H A D	5lgs_qvr.sdf	`108 N54`
/dports/biology/molden/molden5.8/plush/
H A D	7NH	`28 lab="N54" NH="2"`
H A D	D71	`9 lab="N54" NH="0"`

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