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Searched refs:NDTR1_tR (Results 1 – 25 of 62) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c407 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c407 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c407 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c407 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c413 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
440 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
479 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c407 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
434 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
473 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/mtd/nand/raw/
H A Dpxa3xx_nand.c423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()

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