/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/sim/axi/ |
H A D | sim_axis_lib.svh | 7 interface axis_t #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant 8 logic [NUM_STREAMS*DWIDTH-1:0] tdata; 9 logic [NUM_STREAMS-1:0] tvalid; 10 logic [NUM_STREAMS-1:0] tlast; 11 logic [NUM_STREAMS-1:0] tready; 27 interface axis_master #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant 28 axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk)); 32 assert (stream < NUM_STREAMS) else 122 interface axis_slave #(parameter DWIDTH = 32, parameter NUM_STREAMS = 1)(input clk); constant 123 axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk)); [all …]
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H A D | sim_cvita_lib.svh | 111 interface cvita_master #(parameter DWIDTH = 64, parameter NUM_STREAMS = 1)(input clk); constant 112 axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk)); 116 assert (stream < NUM_STREAMS) else 258 interface cvita_slave #(parameter DWIDTH = 64, parameter NUM_STREAMS = 1)(input clk); constant 259 axis_t #(.DWIDTH(DWIDTH), .NUM_STREAMS(NUM_STREAMS)) axis(.clk(clk)); 263 assert (stream < NUM_STREAMS) else
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/ |
H A D | pcie_dma_ctrl.v | 24 parameter NUM_STREAMS = 4, constant 41 output reg [NUM_STREAMS-1:0] set_enabled, 42 output reg [NUM_STREAMS-1:0] set_clear, 43 output [(NUM_STREAMS*FRAME_SIZE_W)-1:0] set_frame_size, 45 input [NUM_STREAMS-1:0] packet_stb, 46 input [NUM_STREAMS-1:0] sample_stb, 47 input [NUM_STREAMS-1:0] stream_busy, 48 input [NUM_STREAMS-1:0] stream_err, 82 reg [31:0] pkt_count_mem[0:NUM_STREAMS-1]; 83 reg [31:0] samp_count_mem[0:NUM_STREAMS-1]; [all …]
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H A D | pcie_dma_ctrl_tb.v | 80 .NUM_STREAMS(4), .FRAME_SIZE_W(16),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/sim/rfnoc/ |
H A D | sim_rfnoc_lib.svh | 108 .NUM_BUSES(NUM_STREAMS)) 116 axis_slave #(.DWIDTH(AXIS_DWIDTH), .NUM_STREAMS(NUM_STREAMS)) s_axis_data(.clk(clk)); 118 logic [15:0] src_sid[0:NUM_STREAMS-1] = '{NUM_STREAMS{16'd0}}; 119 logic [15:0] dst_sid[0:NUM_STREAMS-1] = '{NUM_STREAMS{16'd0}}; 121 logic [11:0] data_seqnum[0:NUM_STREAMS-1] = '{NUM_STREAMS{12'd0}}; 122 int unsigned spp[0:NUM_STREAMS-1] = '{NUM_STREAMS{0}}; 123 int unsigned ticks_per_word[0:NUM_STREAMS-1] = '{NUM_STREAMS{1}}; 124 bit upstream_connected[0:NUM_STREAMS-1] = '{NUM_STREAMS{0}}; 125 bit downstream_connected[0:NUM_STREAMS-1] = '{NUM_STREAMS{0}}; 270 data_seqnum[0:NUM_STREAMS-1] = '{NUM_STREAMS{12'd0}}; [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/zynq_fifo/ |
H A D | zf_arbiter.v | 62 localparam NUM_STREAMS = (1 << STREAMS_WIDTH); constant 67 reg [31:0] rb_data_i [NUM_STREAMS-1:0]; 71 wire [72:0] cmd_data_i [NUM_STREAMS-1:0]; 73 wire cmd_tvalid_i [NUM_STREAMS-1:0]; 74 wire sts_tready_i [NUM_STREAMS-1:0]; 97 if (int_stream_sel < NUM_STREAMS-1) begin 154 for (i=0; i < NUM_STREAMS; i=i+1) begin : stream_circuit
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/dports/graphics/opencv/opencv-4.5.3/contrib/modules/cudaimgproc/test/ |
H A D | test_canny.cpp | 119 #define NUM_STREAMS 128 macro 143 cv::cuda::GpuMat edges[NUM_STREAMS]; in CUDA_TEST_P() 144 …cv::parallel_for_(cv::Range(0, NUM_STREAMS), CannyAsyncParallelLoopBody(d_img_roi, edges, low_thre… in CUDA_TEST_P() 147 for (int i = 0; i < NUM_STREAMS; i++) in CUDA_TEST_P()
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/dports/devel/aws-c-http/aws-c-http-0.6.8/tests/ |
H A D | test_h2_client.c | 1275 for (size_t i = 0; i < NUM_STREAMS; i++) { in TEST_CASE() 1317 for (size_t i = 0; i < NUM_STREAMS; i++) { in TEST_CASE() 1520 enum { NUM_STREAMS = 3 }; in TEST_CASE() enumerator 1543 for (size_t i = 0; i < NUM_STREAMS; ++i) { in TEST_CASE() 1566 size_t end_stream_tick[NUM_STREAMS]; in TEST_CASE() 1567 while (end_stream_count < NUM_STREAMS) { in TEST_CASE() 1607 for (size_t i = 1; i < NUM_STREAMS; ++i) { in TEST_CASE() 1624 for (size_t i = 0; i < NUM_STREAMS; ++i) { in TEST_CASE() 1961 enum { NUM_STREAMS = 2 }; in TEST_CASE() enumerator 2088 enum { NUM_STREAMS = 3 }; in TEST_CASE() enumerator [all …]
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H A D | test_h1_client.c | 2079 enum { NUM_STREAMS = 3 }; in H1_CLIENT_TEST_CASE() enumerator 2080 struct aws_http_message *requests[NUM_STREAMS]; in H1_CLIENT_TEST_CASE() 2082 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() 2131 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() 2148 enum { NUM_STREAMS = 3 }; in H1_CLIENT_TEST_CASE() enumerator 2151 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() 2213 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() 2230 enum { NUM_STREAMS = 3 }; in H1_CLIENT_TEST_CASE() enumerator 2233 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() 2251 for (size_t i = 0; i < NUM_STREAMS; ++i) { in H1_CLIENT_TEST_CASE() [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_fifo/ |
H A D | axi_fifo_tb.sv | 35 axis_master #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) m_axis(.clk(clk)); 36 axis_slave #(.DWIDTH(32), .NUM_STREAMS(NUM_FIFOS)) s_axis(.clk(clk));
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/dports/devel/libspice-server/spice-0.15.0/server/ |
H A D | display-limits.h | 26 #define NUM_STREAMS 50 macro
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H A D | dcc-private.h | 66 VideoStreamAgent stream_agents[NUM_STREAMS];
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H A D | display-channel-private.h | 109 VideoStream streams_buf[NUM_STREAMS];
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H A D | dcc.cpp | 342 for (i = 0; i < NUM_STREAMS; i++) { in dcc_init_stream_agents() 447 for (i = 0; i < NUM_STREAMS; i++) { in dcc_destroy_stream_agents() 855 if (report->stream_id >= NUM_STREAMS) { in dcc_handle_stream_report()
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H A D | stream-channel.cpp | 424 stream_id = (stream_id + 1) % NUM_STREAMS; in change_format()
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H A D | video-stream.cpp | 136 for (i = 0; i < NUM_STREAMS; i++) { in display_channel_init_video_streams() 591 for (i = 0; i < NUM_STREAMS; i++) { in dcc_update_streams_max_latency()
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/dports/cad/veroroute/VeroRoute/Src/ |
H A D | GWriter.h | 33 static const int NUM_STREAMS = 8; variable 151 GStream m_os[NUM_STREAMS]; // Output file streams
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H A D | GWriter.cpp | 577 for (int i = 0; i < NUM_STREAMS && bOK; i++) in Open() 589 for (int i = 0; i < NUM_STREAMS; i++) m_os[i].Close(); in Close()
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/io_port2/pcie_dma_ctrl/ |
H A D | pcie_dma_ctrl_tb.v | 80 .NUM_STREAMS(4), .FRAME_SIZE_W(16),
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/dports/archivers/rzip/rzip-2.1/ |
H A D | rzip.h | 22 #define NUM_STREAMS 2 macro
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H A D | runzip.c | 148 ss = open_stream_in(fd_in, NUM_STREAMS); in runzip_chunk()
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/dports/graphics/opencv/opencv-4.5.3/contrib/modules/cudaoptflow/test/ |
H A D | test_optflow.cpp | 433 #define NUM_STREAMS 16 macro 461 cv::cuda::GpuMat d_flow[NUM_STREAMS]; in CUDA_TEST_P() 462 …cv::parallel_for_(cv::Range(0, NUM_STREAMS), TVL1AsyncParallelLoopBody(loadMat(frame0), loadMat(fr… in CUDA_TEST_P() 465 for (int i = 0; i < NUM_STREAMS; i++) in CUDA_TEST_P()
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/crossbar_tb/ |
H A D | crossbar_tb.sv | 70 axis_t #(.DWIDTH(ROUTER_DWIDTH), .NUM_STREAMS(ROUTER_PORTS)) src2rtr_axis (.clk(clk)); 71 axis_t #(.DWIDTH(ROUTER_DWIDTH), .NUM_STREAMS(ROUTER_PORTS)) rtr2snk_axis (.clk(clk));
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_pcie_int.v | 218 .NUM_STREAMS(NUM_TX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH), 230 .NUM_STREAMS(NUM_RX_STREAMS), .FRAME_SIZE_W(DMA_FRAME_SIZE_WIDTH),
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/dports/archivers/lrzip/lrzip-0.631/ |
H A D | lrzip_private.h | 25 #define NUM_STREAMS 2 macro
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