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Searched refs:NV04_PFIFO_CACHE1_PULL0 (Results 1 – 25 of 27) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv04.c59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); in nv04_fifo_pause()
76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
216 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
305 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
355 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
H A Ddmanv04.c95 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_dma_fini()
117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_dma_fini()
H A Dnv17.c76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
H A Dregsnv04.h114 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
H A Dnv40.c107 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv40_fifo_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv04.c59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); in nv04_fifo_pause()
76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
216 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
305 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
355 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
H A Ddmanv04.c95 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_dma_fini()
117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_dma_fini()
H A Dnv17.c76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
H A Dregsnv04.h114 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
H A Dnv40.c107 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv40_fifo_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv04.c59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); in nv04_fifo_pause()
76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
216 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
305 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
355 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
H A Ddmanv04.c95 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_dma_fini()
117 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_dma_fini()
H A Dnv17.c76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
H A Dregsnv04.h114 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
H A Dnv40.c107 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv40_fifo_init()
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/fifo/
H A Dnouveau_engine_fifo_nv04.c213 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); in nv04_fifo_chan_fini()
233 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_chan_fini()
310 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
321 if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0, in nv04_fifo_pause()
325 if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
339 nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
450 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
537 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
635 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
H A Dnv04.h115 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
H A Dnouveau_engine_fifo_nv17.c199 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
H A Dnouveau_engine_fifo_nv40.c341 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv40_fifo_init()
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm/dist/shared-core/
H A Dnouveau_fifo.c125 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); in nouveau_fifo_init()
152 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); in nouveau_fifo_init()
340 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); in nouveau_fifo_alloc()
383 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); in nouveau_fifo_alloc()
450 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); in nouveau_fifo_free()
463 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); in nouveau_fifo_free()
H A Dnouveau_state.c766 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); in nouveau_suspend()
793 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); in nouveau_suspend()
843 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000); in nouveau_resume()
869 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001); in nouveau_resume()
H A Dnouveau_reg.h522 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
H A Dnouveau_irq.c103 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1); in nouveau_fifo_irq_handler()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h550 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h550 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 macro

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