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Searched refs:NVICState (Results 1 – 25 of 27) sorted by relevance

12

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darmv7m_nvic.c381 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
402 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
409 NVICState *s = opaque; in armv7m_nvic_raw_execution_priority()
490 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
527 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
661 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
693 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
714 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
752 NVICState *s = opaque; in set_irq_level()
1779 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darmv7m_nvic.c404 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
425 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
513 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
550 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
689 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
780 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
812 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
833 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
921 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2154 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
21 DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
40 struct NVICState { struct
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
21 DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
40 struct NVICState { struct
/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darmv7m_nvic.c389 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
410 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
498 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
535 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
674 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
765 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
797 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
818 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
906 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2098 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darmv7m_nvic.c402 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
423 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
511 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
548 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
687 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
778 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
820 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
836 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
929 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2224 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darmv7m_nvic.c389 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
410 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
498 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
535 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
674 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
765 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
797 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
818 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
906 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2098 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darmv7m_nvic.c389 NVICState *s = opaque;
410 NVICState *s = opaque;
498 NVICState *s = (NVICState *)opaque;
535 NVICState *s = (NVICState *)opaque;
674 NVICState *s = (NVICState *)opaque;
765 NVICState *s = (NVICState *)opaque;
797 NVICState *s = (NVICState *)opaque;
818 NVICState *s = (NVICState *)opaque;
906 NVICState *s = (NVICState *)opaque;
2098 NVICState *s = (NVICState *)opaque;
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darmv7m_nvic.c389 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
410 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
498 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
535 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
674 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
765 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
797 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
818 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
906 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2098 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darmv7m_nvic.c402 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
423 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
511 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
548 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
687 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
778 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
820 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
836 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
929 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2224 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
21 DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
40 struct NVICState { struct
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darmv7m_nvic.c404 NVICState *s = opaque; in armv7m_nvic_neg_prio_requested()
425 NVICState *s = opaque; in armv7m_nvic_can_take_pending_exception()
513 NVICState *s = (NVICState *)opaque; in armv7m_nvic_clear_pending()
550 NVICState *s = (NVICState *)opaque; in do_armv7m_nvic_set_pending()
689 NVICState *s = (NVICState *)opaque; in armv7m_nvic_set_pending_lazyfp()
780 NVICState *s = (NVICState *)opaque; in armv7m_nvic_acknowledge_irq()
812 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_pending_irq_info()
833 NVICState *s = (NVICState *)opaque; in armv7m_nvic_complete_irq()
926 NVICState *s = (NVICState *)opaque; in armv7m_nvic_get_ready_status()
2209 NVICState *s = (NVICState *)opaque; in nvic_sysreg_read()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Darmv7m_nvic.h20 typedef struct NVICState NVICState; typedef
21 DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
40 struct NVICState { struct
/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
38 typedef struct NVICState { struct
91 } NVICState; argument
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/
H A Darmv7m_nvic.h20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
38 typedef struct NVICState { struct
91 } NVICState; typedef
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/
H A Darmv7m_nvic.h20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
38 typedef struct NVICState { struct
91 } NVICState; argument
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/
H A Darmv7m_nvic.h20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
38 typedef struct NVICState { struct
91 } NVICState; argument
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/intc/
H A Darmv7m_nvic.h20 OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
38 typedef struct NVICState { struct
91 } NVICState; argument
/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/
H A Darmv7m.h57 NVICState nvic;
/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/
H A Darmv7m.h57 NVICState nvic;
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Darmv7m.h52 NVICState nvic;
/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Darmv7m.h54 NVICState nvic;
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/
H A Darmv7m.h54 NVICState nvic;
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/
H A Darmv7m.h54 NVICState nvic;
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/
H A Darmv7m.h54 NVICState nvic;

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