1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 //***************************************************************************** 37 // 38 // hw_nvic.h - Macros used when accessing the NVIC hardware. 39 // 40 //***************************************************************************** 41 42 #ifndef __HW_NVIC_H__ 43 #define __HW_NVIC_H__ 44 45 //***************************************************************************** 46 // 47 // The following are defines for the NVIC register addresses. 48 // 49 //***************************************************************************** 50 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg 51 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 52 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 53 // Register 54 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 55 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 56 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg 57 58 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 59 #define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable 60 #define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable 61 #define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable 62 #define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable 63 #define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable 64 65 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 66 #define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable 67 68 #define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable 69 #define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable 70 #define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable 71 #define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable 72 73 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 74 #define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending 75 76 #define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending 77 #define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending 78 #define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending 79 #define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending 80 81 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 82 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending 83 84 #define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending 85 #define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending 86 #define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending 87 #define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending 88 89 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 90 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit 91 92 #define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit 93 #define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit 94 #define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit 95 #define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit 96 97 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 98 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 99 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 100 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 101 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 102 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 103 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 104 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 105 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 106 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 107 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 108 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 109 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 110 #define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority 111 112 #define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority 113 #define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority 114 #define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority 115 #define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority 116 #define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority 117 #define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority 118 #define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority 119 #define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority 120 #define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority 121 #define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority 122 #define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority 123 #define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority 124 #define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority 125 #define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority 126 #define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority 127 #define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority 128 #define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority 129 #define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority 130 #define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority 131 #define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority 132 #define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority 133 #define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority 134 #define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority 135 #define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority 136 #define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority 137 #define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority 138 #define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority 139 #define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority 140 #define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority 141 #define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority 142 #define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority 143 #define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority 144 #define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority 145 #define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority 146 #define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority 147 148 149 150 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 151 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 152 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 153 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 154 // Control 155 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 156 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 157 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 158 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 159 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 160 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 161 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 162 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 163 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 164 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 165 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 166 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 167 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 168 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 169 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 170 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 171 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 172 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 173 // Alias 1 174 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 175 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 176 // Alias 2 177 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 178 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 179 // Alias 3 180 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 181 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 182 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 183 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 184 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the NVIC_INT_TYPE register. 189 // 190 //***************************************************************************** 191 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) 192 #define NVIC_INT_TYPE_LINES_S 0 193 194 //***************************************************************************** 195 // 196 // The following are defines for the bit fields in the NVIC_ACTLR register. 197 // 198 //***************************************************************************** 199 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 200 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 201 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 202 // Cycle Instructions 203 204 //***************************************************************************** 205 // 206 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 207 // 208 //***************************************************************************** 209 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 210 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 211 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 212 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 213 214 //***************************************************************************** 215 // 216 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 217 // 218 //***************************************************************************** 219 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 220 #define NVIC_ST_RELOAD_S 0 221 222 //***************************************************************************** 223 // 224 // The following are defines for the bit fields in the NVIC_ST_CURRENT 225 // register. 226 // 227 //***************************************************************************** 228 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 229 #define NVIC_ST_CURRENT_S 0 230 231 //***************************************************************************** 232 // 233 // The following are defines for the bit fields in the NVIC_ST_CAL register. 234 // 235 //***************************************************************************** 236 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock 237 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew 238 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value 239 #define NVIC_ST_CAL_ONEMS_S 0 240 241 //***************************************************************************** 242 // 243 // The following are defines for the bit fields in the NVIC_EN0 register. 244 // 245 //***************************************************************************** 246 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 247 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable 248 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable 249 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable 250 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable 251 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable 252 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable 253 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable 254 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable 255 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable 256 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable 257 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable 258 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable 259 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable 260 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable 261 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable 262 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable 263 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable 264 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable 265 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable 266 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable 267 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable 268 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable 269 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable 270 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable 271 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable 272 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable 273 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable 274 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable 275 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable 276 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable 277 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable 278 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable 279 280 //***************************************************************************** 281 // 282 // The following are defines for the bit fields in the NVIC_EN1 register. 283 // 284 //***************************************************************************** 285 #define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable 286 287 #undef NVIC_EN1_INT_M 288 #define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable 289 290 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable 291 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable 292 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable 293 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable 294 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable 295 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable 296 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable 297 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable 298 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable 299 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable 300 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable 301 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable 302 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable 303 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable 304 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable 305 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable 306 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable 307 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable 308 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable 309 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable 310 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable 311 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable 312 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable 313 314 315 //***************************************************************************** 316 // 317 // The following are defines for the bit fields in the NVIC_EN2 register. 318 // 319 //***************************************************************************** 320 #define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable 321 322 //***************************************************************************** 323 // 324 // The following are defines for the bit fields in the NVIC_EN3 register. 325 // 326 //***************************************************************************** 327 #define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable 328 329 //***************************************************************************** 330 // 331 // The following are defines for the bit fields in the NVIC_EN4 register. 332 // 333 //***************************************************************************** 334 #define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable 335 336 337 //***************************************************************************** 338 // 339 // The following are defines for the bit fields in the NVIC_DIS0 register. 340 // 341 //***************************************************************************** 342 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 343 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable 344 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable 345 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable 346 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable 347 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable 348 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable 349 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable 350 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable 351 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable 352 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable 353 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable 354 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable 355 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable 356 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable 357 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable 358 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable 359 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable 360 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable 361 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable 362 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable 363 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable 364 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable 365 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable 366 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable 367 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable 368 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable 369 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable 370 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable 371 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable 372 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable 373 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable 374 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable 375 376 //***************************************************************************** 377 // 378 // The following are defines for the bit fields in the NVIC_DIS1 register. 379 // 380 //***************************************************************************** 381 #define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable 382 383 #undef NVIC_DIS1_INT_M 384 #define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable 385 386 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable 387 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable 388 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable 389 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable 390 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable 391 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable 392 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable 393 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable 394 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable 395 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable 396 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable 397 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable 398 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable 399 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable 400 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable 401 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable 402 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable 403 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable 404 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable 405 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable 406 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable 407 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable 408 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable 409 #define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable 410 411 412 //***************************************************************************** 413 // 414 // The following are defines for the bit fields in the NVIC_DIS2 register. 415 // 416 //***************************************************************************** 417 #define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable 418 419 //***************************************************************************** 420 // 421 // The following are defines for the bit fields in the NVIC_DIS3 register. 422 // 423 //***************************************************************************** 424 #define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable 425 426 //***************************************************************************** 427 // 428 // The following are defines for the bit fields in the NVIC_DIS4 register. 429 // 430 //***************************************************************************** 431 #define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable 432 433 434 //***************************************************************************** 435 // 436 // The following are defines for the bit fields in the NVIC_PEND0 register. 437 // 438 //***************************************************************************** 439 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 440 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend 441 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend 442 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend 443 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend 444 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend 445 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend 446 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend 447 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend 448 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend 449 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend 450 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend 451 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend 452 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend 453 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend 454 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend 455 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend 456 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend 457 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend 458 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend 459 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend 460 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend 461 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend 462 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend 463 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend 464 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend 465 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend 466 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend 467 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend 468 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend 469 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend 470 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend 471 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend 472 473 //***************************************************************************** 474 // 475 // The following are defines for the bit fields in the NVIC_PEND1 register. 476 // 477 //***************************************************************************** 478 #define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending 479 480 #undef NVIC_PEND1_INT_M 481 #define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending 482 483 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend 484 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend 485 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend 486 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend 487 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend 488 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend 489 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend 490 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend 491 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend 492 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend 493 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend 494 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend 495 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend 496 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend 497 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend 498 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend 499 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend 500 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend 501 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend 502 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend 503 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend 504 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend 505 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend 506 #define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend 507 508 509 //***************************************************************************** 510 // 511 // The following are defines for the bit fields in the NVIC_PEND2 register. 512 // 513 //***************************************************************************** 514 #define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending 515 516 //***************************************************************************** 517 // 518 // The following are defines for the bit fields in the NVIC_PEND3 register. 519 // 520 //***************************************************************************** 521 #define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending 522 523 //***************************************************************************** 524 // 525 // The following are defines for the bit fields in the NVIC_PEND4 register. 526 // 527 //***************************************************************************** 528 #define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending 529 530 531 //***************************************************************************** 532 // 533 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 534 // 535 //***************************************************************************** 536 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 537 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend 538 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend 539 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend 540 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend 541 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend 542 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend 543 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend 544 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend 545 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend 546 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend 547 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend 548 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend 549 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend 550 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend 551 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend 552 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend 553 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend 554 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend 555 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend 556 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend 557 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend 558 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend 559 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend 560 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend 561 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend 562 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend 563 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend 564 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend 565 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend 566 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend 567 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend 568 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend 569 570 //***************************************************************************** 571 // 572 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 573 // 574 //***************************************************************************** 575 #define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending 576 577 #undef NVIC_UNPEND1_INT_M 578 #define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending 579 580 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend 581 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend 582 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend 583 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend 584 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend 585 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend 586 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend 587 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend 588 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend 589 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend 590 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend 591 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend 592 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend 593 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend 594 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend 595 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend 596 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend 597 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend 598 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend 599 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend 600 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend 601 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend 602 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend 603 #define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend 604 605 606 //***************************************************************************** 607 // 608 // The following are defines for the bit fields in the NVIC_UNPEND2 register. 609 // 610 //***************************************************************************** 611 #define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending 612 613 //***************************************************************************** 614 // 615 // The following are defines for the bit fields in the NVIC_UNPEND3 register. 616 // 617 //***************************************************************************** 618 #define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending 619 620 //***************************************************************************** 621 // 622 // The following are defines for the bit fields in the NVIC_UNPEND4 register. 623 // 624 //***************************************************************************** 625 #define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending 626 627 628 //***************************************************************************** 629 // 630 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 631 // 632 //***************************************************************************** 633 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 634 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active 635 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active 636 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active 637 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active 638 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active 639 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active 640 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active 641 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active 642 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active 643 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active 644 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active 645 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active 646 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active 647 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active 648 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active 649 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active 650 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active 651 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active 652 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active 653 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active 654 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active 655 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active 656 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active 657 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active 658 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active 659 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active 660 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active 661 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active 662 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active 663 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active 664 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active 665 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active 666 667 //***************************************************************************** 668 // 669 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 670 // 671 //***************************************************************************** 672 #define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active 673 674 #undef NVIC_ACTIVE1_INT_M 675 #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active 676 677 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active 678 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active 679 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active 680 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active 681 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active 682 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active 683 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active 684 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active 685 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active 686 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active 687 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active 688 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active 689 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active 690 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active 691 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active 692 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active 693 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active 694 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active 695 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active 696 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active 697 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active 698 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active 699 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active 700 #define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active 701 702 703 //***************************************************************************** 704 // 705 // The following are defines for the bit fields in the NVIC_ACTIVE2 register. 706 // 707 //***************************************************************************** 708 #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active 709 710 //***************************************************************************** 711 // 712 // The following are defines for the bit fields in the NVIC_ACTIVE3 register. 713 // 714 //***************************************************************************** 715 #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active 716 717 //***************************************************************************** 718 // 719 // The following are defines for the bit fields in the NVIC_ACTIVE4 register. 720 // 721 //***************************************************************************** 722 #define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active 723 724 725 //***************************************************************************** 726 // 727 // The following are defines for the bit fields in the NVIC_PRI0 register. 728 // 729 //***************************************************************************** 730 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 731 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 732 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 733 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 734 #define NVIC_PRI0_INT3_S 29 735 #define NVIC_PRI0_INT2_S 21 736 #define NVIC_PRI0_INT1_S 13 737 #define NVIC_PRI0_INT0_S 5 738 739 //***************************************************************************** 740 // 741 // The following are defines for the bit fields in the NVIC_PRI1 register. 742 // 743 //***************************************************************************** 744 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 745 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 746 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 747 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 748 #define NVIC_PRI1_INT7_S 29 749 #define NVIC_PRI1_INT6_S 21 750 #define NVIC_PRI1_INT5_S 13 751 #define NVIC_PRI1_INT4_S 5 752 753 //***************************************************************************** 754 // 755 // The following are defines for the bit fields in the NVIC_PRI2 register. 756 // 757 //***************************************************************************** 758 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 759 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 760 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 761 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 762 #define NVIC_PRI2_INT11_S 29 763 #define NVIC_PRI2_INT10_S 21 764 #define NVIC_PRI2_INT9_S 13 765 #define NVIC_PRI2_INT8_S 5 766 767 //***************************************************************************** 768 // 769 // The following are defines for the bit fields in the NVIC_PRI3 register. 770 // 771 //***************************************************************************** 772 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 773 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 774 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 775 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 776 #define NVIC_PRI3_INT15_S 29 777 #define NVIC_PRI3_INT14_S 21 778 #define NVIC_PRI3_INT13_S 13 779 #define NVIC_PRI3_INT12_S 5 780 781 //***************************************************************************** 782 // 783 // The following are defines for the bit fields in the NVIC_PRI4 register. 784 // 785 //***************************************************************************** 786 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 787 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 788 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 789 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 790 #define NVIC_PRI4_INT19_S 29 791 #define NVIC_PRI4_INT18_S 21 792 #define NVIC_PRI4_INT17_S 13 793 #define NVIC_PRI4_INT16_S 5 794 795 //***************************************************************************** 796 // 797 // The following are defines for the bit fields in the NVIC_PRI5 register. 798 // 799 //***************************************************************************** 800 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 801 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 802 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 803 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 804 #define NVIC_PRI5_INT23_S 29 805 #define NVIC_PRI5_INT22_S 21 806 #define NVIC_PRI5_INT21_S 13 807 #define NVIC_PRI5_INT20_S 5 808 809 //***************************************************************************** 810 // 811 // The following are defines for the bit fields in the NVIC_PRI6 register. 812 // 813 //***************************************************************************** 814 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 815 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 816 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 817 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 818 #define NVIC_PRI6_INT27_S 29 819 #define NVIC_PRI6_INT26_S 21 820 #define NVIC_PRI6_INT25_S 13 821 #define NVIC_PRI6_INT24_S 5 822 823 //***************************************************************************** 824 // 825 // The following are defines for the bit fields in the NVIC_PRI7 register. 826 // 827 //***************************************************************************** 828 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 829 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 830 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 831 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 832 #define NVIC_PRI7_INT31_S 29 833 #define NVIC_PRI7_INT30_S 21 834 #define NVIC_PRI7_INT29_S 13 835 #define NVIC_PRI7_INT28_S 5 836 837 //***************************************************************************** 838 // 839 // The following are defines for the bit fields in the NVIC_PRI8 register. 840 // 841 //***************************************************************************** 842 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 843 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 844 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 845 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 846 #define NVIC_PRI8_INT35_S 29 847 #define NVIC_PRI8_INT34_S 21 848 #define NVIC_PRI8_INT33_S 13 849 #define NVIC_PRI8_INT32_S 5 850 851 //***************************************************************************** 852 // 853 // The following are defines for the bit fields in the NVIC_PRI9 register. 854 // 855 //***************************************************************************** 856 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 857 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 858 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 859 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 860 #define NVIC_PRI9_INT39_S 29 861 #define NVIC_PRI9_INT38_S 21 862 #define NVIC_PRI9_INT37_S 13 863 #define NVIC_PRI9_INT36_S 5 864 865 //***************************************************************************** 866 // 867 // The following are defines for the bit fields in the NVIC_PRI10 register. 868 // 869 //***************************************************************************** 870 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 871 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 872 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 873 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 874 #define NVIC_PRI10_INT43_S 29 875 #define NVIC_PRI10_INT42_S 21 876 #define NVIC_PRI10_INT41_S 13 877 #define NVIC_PRI10_INT40_S 5 878 879 //***************************************************************************** 880 // 881 // The following are defines for the bit fields in the NVIC_PRI11 register. 882 // 883 //***************************************************************************** 884 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 885 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 886 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 887 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 888 #define NVIC_PRI11_INT47_S 29 889 #define NVIC_PRI11_INT46_S 21 890 #define NVIC_PRI11_INT45_S 13 891 #define NVIC_PRI11_INT44_S 5 892 893 //***************************************************************************** 894 // 895 // The following are defines for the bit fields in the NVIC_PRI12 register. 896 // 897 //***************************************************************************** 898 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 899 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 900 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 901 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 902 #define NVIC_PRI12_INT51_S 29 903 #define NVIC_PRI12_INT50_S 21 904 #define NVIC_PRI12_INT49_S 13 905 #define NVIC_PRI12_INT48_S 5 906 907 //***************************************************************************** 908 // 909 // The following are defines for the bit fields in the NVIC_PRI13 register. 910 // 911 //***************************************************************************** 912 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 913 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 914 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 915 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 916 #define NVIC_PRI13_INT55_S 29 917 #define NVIC_PRI13_INT54_S 21 918 #define NVIC_PRI13_INT53_S 13 919 #define NVIC_PRI13_INT52_S 5 920 921 922 //***************************************************************************** 923 // 924 // The following are defines for the bit fields in the NVIC_PRI14 register. 925 // 926 //***************************************************************************** 927 #define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask 928 #define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask 929 #define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask 930 #define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask 931 #define NVIC_PRI14_INTD_S 29 932 #define NVIC_PRI14_INTC_S 21 933 #define NVIC_PRI14_INTB_S 13 934 #define NVIC_PRI14_INTA_S 5 935 936 //***************************************************************************** 937 // 938 // The following are defines for the bit fields in the NVIC_PRI15 register. 939 // 940 //***************************************************************************** 941 #define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask 942 #define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask 943 #define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask 944 #define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask 945 #define NVIC_PRI15_INTD_S 29 946 #define NVIC_PRI15_INTC_S 21 947 #define NVIC_PRI15_INTB_S 13 948 #define NVIC_PRI15_INTA_S 5 949 950 //***************************************************************************** 951 // 952 // The following are defines for the bit fields in the NVIC_PRI16 register. 953 // 954 //***************************************************************************** 955 #define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask 956 #define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask 957 #define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask 958 #define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask 959 #define NVIC_PRI16_INTD_S 29 960 #define NVIC_PRI16_INTC_S 21 961 #define NVIC_PRI16_INTB_S 13 962 #define NVIC_PRI16_INTA_S 5 963 964 //***************************************************************************** 965 // 966 // The following are defines for the bit fields in the NVIC_PRI17 register. 967 // 968 //***************************************************************************** 969 #define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask 970 #define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask 971 #define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask 972 #define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask 973 #define NVIC_PRI17_INTD_S 29 974 #define NVIC_PRI17_INTC_S 21 975 #define NVIC_PRI17_INTB_S 13 976 #define NVIC_PRI17_INTA_S 5 977 978 //***************************************************************************** 979 // 980 // The following are defines for the bit fields in the NVIC_PRI18 register. 981 // 982 //***************************************************************************** 983 #define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask 984 #define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask 985 #define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask 986 #define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask 987 #define NVIC_PRI18_INTD_S 29 988 #define NVIC_PRI18_INTC_S 21 989 #define NVIC_PRI18_INTB_S 13 990 #define NVIC_PRI18_INTA_S 5 991 992 //***************************************************************************** 993 // 994 // The following are defines for the bit fields in the NVIC_PRI19 register. 995 // 996 //***************************************************************************** 997 #define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask 998 #define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask 999 #define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask 1000 #define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask 1001 #define NVIC_PRI19_INTD_S 29 1002 #define NVIC_PRI19_INTC_S 21 1003 #define NVIC_PRI19_INTB_S 13 1004 #define NVIC_PRI19_INTA_S 5 1005 1006 //***************************************************************************** 1007 // 1008 // The following are defines for the bit fields in the NVIC_PRI20 register. 1009 // 1010 //***************************************************************************** 1011 #define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask 1012 #define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask 1013 #define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask 1014 #define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask 1015 #define NVIC_PRI20_INTD_S 29 1016 #define NVIC_PRI20_INTC_S 21 1017 #define NVIC_PRI20_INTB_S 13 1018 #define NVIC_PRI20_INTA_S 5 1019 1020 //***************************************************************************** 1021 // 1022 // The following are defines for the bit fields in the NVIC_PRI21 register. 1023 // 1024 //***************************************************************************** 1025 #define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask 1026 #define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask 1027 #define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask 1028 #define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask 1029 #define NVIC_PRI21_INTD_S 29 1030 #define NVIC_PRI21_INTC_S 21 1031 #define NVIC_PRI21_INTB_S 13 1032 #define NVIC_PRI21_INTA_S 5 1033 1034 //***************************************************************************** 1035 // 1036 // The following are defines for the bit fields in the NVIC_PRI22 register. 1037 // 1038 //***************************************************************************** 1039 #define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask 1040 #define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask 1041 #define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask 1042 #define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask 1043 #define NVIC_PRI22_INTD_S 29 1044 #define NVIC_PRI22_INTC_S 21 1045 #define NVIC_PRI22_INTB_S 13 1046 #define NVIC_PRI22_INTA_S 5 1047 1048 //***************************************************************************** 1049 // 1050 // The following are defines for the bit fields in the NVIC_PRI23 register. 1051 // 1052 //***************************************************************************** 1053 #define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask 1054 #define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask 1055 #define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask 1056 #define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask 1057 #define NVIC_PRI23_INTD_S 29 1058 #define NVIC_PRI23_INTC_S 21 1059 #define NVIC_PRI23_INTB_S 13 1060 #define NVIC_PRI23_INTA_S 5 1061 1062 //***************************************************************************** 1063 // 1064 // The following are defines for the bit fields in the NVIC_PRI24 register. 1065 // 1066 //***************************************************************************** 1067 #define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask 1068 #define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask 1069 #define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask 1070 #define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask 1071 #define NVIC_PRI24_INTD_S 29 1072 #define NVIC_PRI24_INTC_S 21 1073 #define NVIC_PRI24_INTB_S 13 1074 #define NVIC_PRI24_INTA_S 5 1075 1076 //***************************************************************************** 1077 // 1078 // The following are defines for the bit fields in the NVIC_PRI25 register. 1079 // 1080 //***************************************************************************** 1081 #define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask 1082 #define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask 1083 #define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask 1084 #define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask 1085 #define NVIC_PRI25_INTD_S 29 1086 #define NVIC_PRI25_INTC_S 21 1087 #define NVIC_PRI25_INTB_S 13 1088 #define NVIC_PRI25_INTA_S 5 1089 1090 //***************************************************************************** 1091 // 1092 // The following are defines for the bit fields in the NVIC_PRI26 register. 1093 // 1094 //***************************************************************************** 1095 #define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask 1096 #define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask 1097 #define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask 1098 #define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask 1099 #define NVIC_PRI26_INTD_S 29 1100 #define NVIC_PRI26_INTC_S 21 1101 #define NVIC_PRI26_INTB_S 13 1102 #define NVIC_PRI26_INTA_S 5 1103 1104 //***************************************************************************** 1105 // 1106 // The following are defines for the bit fields in the NVIC_PRI27 register. 1107 // 1108 //***************************************************************************** 1109 #define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask 1110 #define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask 1111 #define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask 1112 #define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask 1113 #define NVIC_PRI27_INTD_S 29 1114 #define NVIC_PRI27_INTC_S 21 1115 #define NVIC_PRI27_INTB_S 13 1116 #define NVIC_PRI27_INTA_S 5 1117 1118 //***************************************************************************** 1119 // 1120 // The following are defines for the bit fields in the NVIC_PRI28 register. 1121 // 1122 //***************************************************************************** 1123 #define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask 1124 #define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask 1125 #define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask 1126 #define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask 1127 #define NVIC_PRI28_INTD_S 29 1128 #define NVIC_PRI28_INTC_S 21 1129 #define NVIC_PRI28_INTB_S 13 1130 #define NVIC_PRI28_INTA_S 5 1131 1132 //***************************************************************************** 1133 // 1134 // The following are defines for the bit fields in the NVIC_PRI29 register. 1135 // 1136 //***************************************************************************** 1137 #define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask 1138 #define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask 1139 #define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask 1140 #define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask 1141 #define NVIC_PRI29_INTD_S 29 1142 #define NVIC_PRI29_INTC_S 21 1143 #define NVIC_PRI29_INTB_S 13 1144 #define NVIC_PRI29_INTA_S 5 1145 1146 //***************************************************************************** 1147 // 1148 // The following are defines for the bit fields in the NVIC_PRI30 register. 1149 // 1150 //***************************************************************************** 1151 #define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask 1152 #define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask 1153 #define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask 1154 #define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask 1155 #define NVIC_PRI30_INTD_S 29 1156 #define NVIC_PRI30_INTC_S 21 1157 #define NVIC_PRI30_INTB_S 13 1158 #define NVIC_PRI30_INTA_S 5 1159 1160 //***************************************************************************** 1161 // 1162 // The following are defines for the bit fields in the NVIC_PRI31 register. 1163 // 1164 //***************************************************************************** 1165 #define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask 1166 #define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask 1167 #define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask 1168 #define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask 1169 #define NVIC_PRI31_INTD_S 29 1170 #define NVIC_PRI31_INTC_S 21 1171 #define NVIC_PRI31_INTB_S 13 1172 #define NVIC_PRI31_INTA_S 5 1173 1174 //***************************************************************************** 1175 // 1176 // The following are defines for the bit fields in the NVIC_PRI32 register. 1177 // 1178 //***************************************************************************** 1179 #define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask 1180 #define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask 1181 #define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask 1182 #define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask 1183 #define NVIC_PRI32_INTD_S 29 1184 #define NVIC_PRI32_INTC_S 21 1185 #define NVIC_PRI32_INTB_S 13 1186 #define NVIC_PRI32_INTA_S 5 1187 1188 1189 //***************************************************************************** 1190 // 1191 // The following are defines for the bit fields in the NVIC_CPUID register. 1192 // 1193 //***************************************************************************** 1194 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 1195 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 1196 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 1197 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 1198 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 1199 #define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor 1200 1201 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 1202 1203 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 1204 1205 //***************************************************************************** 1206 // 1207 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 1208 // 1209 //***************************************************************************** 1210 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 1211 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 1212 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 1213 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 1214 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 1215 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 1216 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 1217 #define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number 1218 1219 #undef NVIC_INT_CTRL_VEC_PEN_M 1220 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 1221 1222 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 1223 0x00002000 // NMI 1224 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 1225 0x00003000 // Hard fault 1226 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 1227 0x00004000 // Memory management fault 1228 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 1229 0x00005000 // Bus fault 1230 #define NVIC_INT_CTRL_VEC_PEN_USG \ 1231 0x00006000 // Usage fault 1232 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 1233 0x0000B000 // SVCall 1234 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 1235 0x0000E000 // PendSV 1236 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 1237 0x0000F000 // SysTick 1238 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 1239 #define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number 1240 1241 #undef NVIC_INT_CTRL_VEC_ACT_M 1242 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 1243 1244 #define NVIC_INT_CTRL_VEC_PEN_S 12 1245 #define NVIC_INT_CTRL_VEC_ACT_S 0 1246 1247 //***************************************************************************** 1248 // 1249 // The following are defines for the bit fields in the NVIC_VTABLE register. 1250 // 1251 //***************************************************************************** 1252 #define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base 1253 #define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset 1254 1255 #undef NVIC_VTABLE_OFFSET_M 1256 #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset 1257 1258 #define NVIC_VTABLE_OFFSET_S 9 1259 1260 #undef NVIC_VTABLE_OFFSET_S 1261 #define NVIC_VTABLE_OFFSET_S 10 1262 1263 1264 //***************************************************************************** 1265 // 1266 // The following are defines for the bit fields in the NVIC_APINT register. 1267 // 1268 //***************************************************************************** 1269 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 1270 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 1271 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 1272 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 1273 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 1274 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 1275 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 1276 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 1277 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 1278 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 1279 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 1280 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 1281 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 1282 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 1283 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 1284 1285 //***************************************************************************** 1286 // 1287 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 1288 // 1289 //***************************************************************************** 1290 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 1291 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 1292 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 1293 1294 //***************************************************************************** 1295 // 1296 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 1297 // 1298 //***************************************************************************** 1299 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 1300 // Entry 1301 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 1302 // Fault 1303 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 1304 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 1305 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 1306 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 1307 1308 //***************************************************************************** 1309 // 1310 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 1311 // 1312 //***************************************************************************** 1313 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 1314 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 1315 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 1316 #define NVIC_SYS_PRI1_USAGE_S 21 1317 #define NVIC_SYS_PRI1_BUS_S 13 1318 #define NVIC_SYS_PRI1_MEM_S 5 1319 1320 //***************************************************************************** 1321 // 1322 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 1323 // 1324 //***************************************************************************** 1325 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 1326 #define NVIC_SYS_PRI2_SVC_S 29 1327 1328 //***************************************************************************** 1329 // 1330 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 1331 // 1332 //***************************************************************************** 1333 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 1334 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 1335 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 1336 #define NVIC_SYS_PRI3_TICK_S 29 1337 #define NVIC_SYS_PRI3_PENDSV_S 21 1338 #define NVIC_SYS_PRI3_DEBUG_S 5 1339 1340 //***************************************************************************** 1341 // 1342 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 1343 // register. 1344 // 1345 //***************************************************************************** 1346 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 1347 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 1348 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 1349 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 1350 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 1351 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 1352 #define NVIC_SYS_HND_CTRL_USAGEP \ 1353 0x00001000 // Usage Fault Pending 1354 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 1355 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 1356 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 1357 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 1358 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 1359 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 1360 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 1361 1362 //***************************************************************************** 1363 // 1364 // The following are defines for the bit fields in the NVIC_FAULT_STAT 1365 // register. 1366 // 1367 //***************************************************************************** 1368 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 1369 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 1370 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 1371 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 1372 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 1373 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 1374 // Fault 1375 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 1376 1377 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 1378 // State Preservation 1379 1380 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 1381 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 1382 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 1383 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 1384 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 1385 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 1386 // Register Valid 1387 1388 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 1389 // Floating-Point Lazy State 1390 // Preservation 1391 1392 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 1393 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 1394 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 1395 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 1396 1397 //***************************************************************************** 1398 // 1399 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 1400 // register. 1401 // 1402 //***************************************************************************** 1403 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 1404 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 1405 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 1406 1407 //***************************************************************************** 1408 // 1409 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 1410 // register. 1411 // 1412 //***************************************************************************** 1413 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 1414 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 1415 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 1416 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 1417 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 1418 1419 //***************************************************************************** 1420 // 1421 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 1422 // 1423 //***************************************************************************** 1424 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 1425 #define NVIC_MM_ADDR_S 0 1426 1427 //***************************************************************************** 1428 // 1429 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 1430 // register. 1431 // 1432 //***************************************************************************** 1433 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 1434 #define NVIC_FAULT_ADDR_S 0 1435 1436 //***************************************************************************** 1437 // 1438 // The following are defines for the bit fields in the NVIC_MPU_TYPE register. 1439 // 1440 //***************************************************************************** 1441 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions 1442 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions 1443 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU 1444 #define NVIC_MPU_TYPE_IREGION_S 16 1445 #define NVIC_MPU_TYPE_DREGION_S 8 1446 1447 //***************************************************************************** 1448 // 1449 // The following are defines for the bit fields in the NVIC_MPU_CTRL register. 1450 // 1451 //***************************************************************************** 1452 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region 1453 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults 1454 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable 1455 1456 //***************************************************************************** 1457 // 1458 // The following are defines for the bit fields in the NVIC_MPU_NUMBER 1459 // register. 1460 // 1461 //***************************************************************************** 1462 #define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access 1463 #define NVIC_MPU_NUMBER_S 0 1464 1465 //***************************************************************************** 1466 // 1467 // The following are defines for the bit fields in the NVIC_MPU_BASE register. 1468 // 1469 //***************************************************************************** 1470 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask 1471 #define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid 1472 #define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number 1473 #define NVIC_MPU_BASE_ADDR_S 5 1474 #define NVIC_MPU_BASE_REGION_S 0 1475 1476 //***************************************************************************** 1477 // 1478 // The following are defines for the bit fields in the NVIC_MPU_ATTR register. 1479 // 1480 //***************************************************************************** 1481 #define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes 1482 #define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable 1483 #define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege 1484 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access 1485 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none 1486 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only 1487 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw 1488 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none 1489 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro 1490 #define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask 1491 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable 1492 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable 1493 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable 1494 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits 1495 #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable 1496 #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable 1497 #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable 1498 #define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable 1499 #define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable 1500 #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable 1501 #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable 1502 #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable 1503 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask 1504 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes 1505 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes 1506 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes 1507 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes 1508 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes 1509 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes 1510 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes 1511 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes 1512 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes 1513 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes 1514 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes 1515 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes 1516 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes 1517 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes 1518 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes 1519 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes 1520 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes 1521 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes 1522 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes 1523 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes 1524 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes 1525 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes 1526 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes 1527 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes 1528 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes 1529 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes 1530 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes 1531 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes 1532 #define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable 1533 1534 //***************************************************************************** 1535 // 1536 // The following are defines for the bit fields in the NVIC_MPU_BASE1 register. 1537 // 1538 //***************************************************************************** 1539 #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask 1540 #define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid 1541 #define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number 1542 #define NVIC_MPU_BASE1_ADDR_S 5 1543 #define NVIC_MPU_BASE1_REGION_S 0 1544 1545 //***************************************************************************** 1546 // 1547 // The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. 1548 // 1549 //***************************************************************************** 1550 #define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable 1551 #define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege 1552 #define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask 1553 #define NVIC_MPU_ATTR1_SHAREABLE \ 1554 0x00040000 // Shareable 1555 #define NVIC_MPU_ATTR1_CACHEABLE \ 1556 0x00020000 // Cacheable 1557 #define NVIC_MPU_ATTR1_BUFFRABLE \ 1558 0x00010000 // Bufferable 1559 #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits 1560 #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask 1561 #define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable 1562 1563 //***************************************************************************** 1564 // 1565 // The following are defines for the bit fields in the NVIC_MPU_BASE2 register. 1566 // 1567 //***************************************************************************** 1568 #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask 1569 #define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid 1570 #define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number 1571 #define NVIC_MPU_BASE2_ADDR_S 5 1572 #define NVIC_MPU_BASE2_REGION_S 0 1573 1574 //***************************************************************************** 1575 // 1576 // The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. 1577 // 1578 //***************************************************************************** 1579 #define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable 1580 #define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege 1581 #define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask 1582 #define NVIC_MPU_ATTR2_SHAREABLE \ 1583 0x00040000 // Shareable 1584 #define NVIC_MPU_ATTR2_CACHEABLE \ 1585 0x00020000 // Cacheable 1586 #define NVIC_MPU_ATTR2_BUFFRABLE \ 1587 0x00010000 // Bufferable 1588 #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits 1589 #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask 1590 #define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable 1591 1592 //***************************************************************************** 1593 // 1594 // The following are defines for the bit fields in the NVIC_MPU_BASE3 register. 1595 // 1596 //***************************************************************************** 1597 #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask 1598 #define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid 1599 #define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number 1600 #define NVIC_MPU_BASE3_ADDR_S 5 1601 #define NVIC_MPU_BASE3_REGION_S 0 1602 1603 //***************************************************************************** 1604 // 1605 // The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. 1606 // 1607 //***************************************************************************** 1608 #define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable 1609 #define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege 1610 #define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask 1611 #define NVIC_MPU_ATTR3_SHAREABLE \ 1612 0x00040000 // Shareable 1613 #define NVIC_MPU_ATTR3_CACHEABLE \ 1614 0x00020000 // Cacheable 1615 #define NVIC_MPU_ATTR3_BUFFRABLE \ 1616 0x00010000 // Bufferable 1617 #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits 1618 #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask 1619 #define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable 1620 1621 //***************************************************************************** 1622 // 1623 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 1624 // 1625 //***************************************************************************** 1626 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 1627 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 1628 #define NVIC_DBG_CTRL_S_RESET_ST \ 1629 0x02000000 // Core has reset since last read 1630 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 1631 0x01000000 // Core has executed insruction 1632 // since last read 1633 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 1634 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 1635 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 1636 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 1637 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 1638 0x00000020 // Breaks a stalled load/store 1639 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 1640 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 1641 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 1642 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 1643 1644 //***************************************************************************** 1645 // 1646 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 1647 // 1648 //***************************************************************************** 1649 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 1650 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 1651 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 1652 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 1653 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 1654 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 1655 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 1656 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 1657 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 1658 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 1659 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 1660 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 1661 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 1662 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 1663 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 1664 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 1665 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 1666 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 1667 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 1668 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 1669 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 1670 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 1671 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 1672 1673 //***************************************************************************** 1674 // 1675 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 1676 // 1677 //***************************************************************************** 1678 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 1679 #define NVIC_DBG_DATA_S 0 1680 1681 //***************************************************************************** 1682 // 1683 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1684 // 1685 //***************************************************************************** 1686 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1687 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1688 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1689 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1690 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1691 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1692 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1693 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1694 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1695 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1696 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1697 1698 //***************************************************************************** 1699 // 1700 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1701 // 1702 //***************************************************************************** 1703 #define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID 1704 1705 #undef NVIC_SW_TRIG_INTID_M 1706 #define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID 1707 1708 #define NVIC_SW_TRIG_INTID_S 0 1709 1710 #endif // __HW_NVIC_H__ 1711