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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
129 RCI.NumRegs = N + CSRAlias.size(); in compute()
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
143 if (StressRA && RCI.NumRegs > StressRA) in compute()
144 RCI.NumRegs = StressRA; in compute()
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
157 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
128 RCI.NumRegs = N + CSRAlias.size(); in compute()
129 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
142 if (StressRA && RCI.NumRegs > StressRA) in compute()
143 RCI.NumRegs = StressRA; in compute()
148 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
156 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp96 unsigned NumRegs = RC->getNumRegs(); in compute() local
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
128 RCI.NumRegs = N + CSRAlias.size(); in compute()
129 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
142 if (StressRA && RCI.NumRegs > StressRA) in compute()
143 RCI.NumRegs = StressRA; in compute()
148 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
156 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp98 unsigned NumRegs = RC->getNumRegs(); in compute() local
101 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
131 RCI.NumRegs = N + CSRAlias.size(); in compute()
132 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
145 if (StressRA && RCI.NumRegs > StressRA) in compute()
146 RCI.NumRegs = StressRA; in compute()
151 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
159 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp90 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
113 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
115 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
119 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
123 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
129 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
130 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
146 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
148 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
150 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h216 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated() argument
217 for (unsigned i = 0; i != NumRegs; ++i) in getFirstUnallocated()
220 return NumRegs; in getFirstUnallocated()
243 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg() argument
244 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
245 if (FirstUnalloc == NumRegs) in AllocateReg()
256 unsigned NumRegs) { in AllocateReg() argument
257 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); in AllocateReg()
258 if (FirstUnalloc == NumRegs) in AllocateReg()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
114 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
116 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
120 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
124 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
131 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
147 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
149 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
151 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
114 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
116 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
120 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
124 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
131 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
147 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
149 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
151 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp91 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
114 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
116 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
120 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
124 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
130 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
131 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
147 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
149 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
151 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp86 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
109 unsigned NumRegs = Intervals.size(); in distanceTo()
111 for (unsigned N = 0; N < NumRegs; ++N) in distanceTo()
115 for (unsigned N = 0; N < NumRegs; ++N) in distanceTo()
119 for (unsigned N = 0; N < NumRegs; ++N) in distanceTo()
125 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const {
126 for (unsigned N = 0; N < NumRegs; ++N) {
142 unsigned NumRegs = Intervals.size();
144 if (NumRegs > MaxNumVGPRs)
146 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0;
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp86 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
109 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
111 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
115 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
119 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
125 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
126 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
142 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
144 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
146 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp86 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
109 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
111 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
115 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
119 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
125 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
126 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
142 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
144 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
146 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
[all …]

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