1 /* CPUINT.H (c) Copyright Jan Jaeger, 2001-2009 */ 2 /* Hercules Interrupt State and Mask Definitions */ 3 4 /********************************************************************** 5 Interrupts_State & Interrupts_Mask bits definition (Initial_Mask=800E) 6 Machine check, PER and external interrupt subclass bit positions 7 are fixed by the architecture and cannot be changed 8 Floating interrupts are made pending to all CPUs, and are 9 recorded in the sysblk structure, CPU specific interrupts 10 are recorded in the regs structure. 11 hi0m mmmm pppp p00p xxxx xxxx xxxx h0hs : type U32 12 || | |||| |||| |--| |||| |||| |||| |-|| h:mask is always '1' 13 || | |||| |||| | | |||| |||| |||| | || s:state is always '1' 14 || | |||| |||| | | |||| |||| |||| | |+--> '1' : PSW_WAIT 15 || | |||| |||| | | |||| |||| |||| | +---> '1' : RESTART 16 || | |||| |||| | | |||| |||| |||| | (available) 17 || | |||| |||| | | |||| |||| |||| +-----> '1' : STORSTAT 18 || | |||| |||| | | |||| |||| |||| 19 || | |||| |||| | | |||| |||| |||+-------> '1' : ETR 20 || | |||| |||| | | |||| |||| ||+--------> '1' : EXTSIG 21 || | |||| |||| | | |||| |||| |+---------> '1' : INTKEY 22 || | |||| |||| | | |||| |||| +----------> '1' : ITIMER 23 || | |||| |||| | | |||| |||| 24 || | |||| |||| | | |||| |||+------------> '1' : ECPS VTIMER 25 || | |||| |||| | | |||| ||+-------------> '1' : SERVSIG 26 || | |||| |||| | | |||| |+--------------> '1' : PTIMER 27 || | |||| |||| | | |||| +---------------> '1' : CLKC 28 || | |||| |||| | | |||| 29 || | |||| |||| | | |||+-----------------> '1' : TODSYNC 30 || | |||| |||| | | ||+------------------> '1' : EXTCALL 31 || | |||| |||| | | |+-------------------> '1' : EMERSIG 32 || | |||| |||| | | +--------------------> '1' : MALFALT 33 || | |||| |||| | | 34 || | |||| |||| | +----------------------> '1' : PER IFNUL 35 || | |||| |||| | 36 || | |||| |||| | 37 || | |||| |||| +-------------------------> '1' : PER STURA 38 || | |||| |||| 39 || | |||| |||+---------------------------> '1' : PER GRA 40 || | |||| ||+----------------------------> '1' : PER SA 41 || | |||| |+-----------------------------> '1' : PER IF 42 || | |||| +------------------------------> '1' : PER SB 43 || | |||| 44 || | |||+--------------------------------> '1' : WARNING 45 || | ||+---------------------------------> '1' : XDMGRPT 46 || | |+----------------------------------> '1' : DGRDRPT 47 || | +-----------------------------------> '1' : RCVYRPT 48 || | 49 || +-------------------------------------> '1' : CHANRPT 50 || 51 |+---------------------------------------> '1' : IO 52 +----------------------------------------> '1' : INTERRUPT possible 53 **********************************************************************/ 54 55 // Hercules internal bit# macro: bit numbers are referenced counting 56 // from the RIGHT to left (i.e. 31 <-- 0) and thus the numerical value 57 // of a set bit is equal to two raised to the power of the bit position. 58 59 // While this is the COMPLETE OPPOSITE from the way bit numbers are 60 // numbered in IBM architectural reference manuals, we do it this way 61 // anyway since that's the way Intel numbers their bits, thus allowing 62 // us to easily replace bit referencing statements with corresponding 63 // Intel assembler bit manipulation instructions (since Intel is still 64 // the predominant host architecture platform for Hercules) 65 66 /* The BIT() macro should only be used for bit numbers 67 strictly less than 32 */ 68 #ifndef BIT 69 #define BIT(nr) ( 1 << (nr) ) // (bit# counting from the right) 70 #endif 71 72 /* The CPU_BIT macro is solely for manipulating 73 the CPU number as a CPU bit in a CPU_BITMAP */ 74 #ifndef CPU_BIT 75 #define CPU_BIT(nr) ( (( CPU_BITMAP ) ( 1 ) ) << ( nr ) ) 76 #endif 77 78 /* Interrupt bit numbers */ 79 #define IC_INTERRUPT 31 /* 0x80000000 */ 80 #define IC_IO 30 /* 0x40000000 */ 81 #define IC_UNUSED_29 29 /* 0x20000000 */ 82 #define IC_CHANRPT 28 /* 0x10000000 - Architecture dependent (CR14) */ 83 #define IC_RCVYRPT 27 /* 0x08000000 - Architecture dependent (CR14) */ 84 #define IC_DGRDRPT 26 /* 0x04000000 - Architecture dependent (CR14) */ 85 #define IC_XDMGRPT 25 /* 0x02000000 - Architecture dependent (CR14) */ 86 #define IC_WARNING 24 /* 0x01000000 - Architecture dependent (CR14) */ 87 #define IC_PER_SB 23 /* 0x00800000 - Architecture dependent (CR9 >> 8) */ 88 #define IC_PER_IF 22 /* 0x00400000 - Architecture dependent (CR9 >> 8) */ 89 #define IC_PER_SA 21 /* 0x00200000 - Architecture dependent (CR9 >> 8) */ 90 #define IC_PER_GRA 20 /* 0x00100000 - Architecture dependent (CR9 >> 8) */ 91 #define IC_PER_STURA 19 /* 0x00080000 - Architecture dependent (CR9 >> 8) */ 92 #define IC_UNUSED_18 18 /* 0x00040000 */ 93 #define IC_UNUSED_17 17 /* 0x00020000 */ 94 #define IC_PER_IFNUL 16 /* 0x00010000 - Architecture dependent (CR9 >> 8) */ 95 #define IC_MALFALT 15 /* 0x00008000 - Architecture dependent (CR0) */ 96 #define IC_EMERSIG 14 /* 0x00004000 - Architecture dependent (CR0) */ 97 #define IC_EXTCALL 13 /* 0x00002000 - Architecture dependent (CR0) */ 98 #define IC_TODSYNC 12 /* 0x00001000 - Architecture dependent (CR0) */ 99 #define IC_CLKC 11 /* 0x00000800 - Architecture dependent (CR0) */ 100 #define IC_PTIMER 10 /* 0x00000400 - Architecture dependent (CR0) */ 101 #define IC_SERVSIG 9 /* 0x00000200 - Architecture dependent (CR0) */ 102 #define IC_ECPSVTIMER 8 /* 0x00000100 - Not Architecture dependent */ 103 #define IC_ITIMER 7 /* 0x00000080 - Architecture dependent (CR0) */ 104 #define IC_INTKEY 6 /* 0x00000040 - Architecture dependent (CR0) */ 105 #define IC_EXTSIG 5 /* 0x00000020 - Architecture dependent (CR0) */ 106 #define IC_ETR 4 /* 0x00000010 - Architecture dependent (CR0) */ 107 #define IC_STORSTAT 3 /* 0x00000008 */ 108 #define IC_UNUSED_2 2 /* 0x00000004 */ 109 #define IC_RESTART 1 /* 0x00000002 */ 110 #define IC_PSW_WAIT 0 /* 0x00000001 */ 111 112 /* Initial values */ 113 #define IC_INITIAL_STATE BIT(IC_PSW_WAIT) 114 #define IC_INITIAL_MASK ( BIT(IC_INTERRUPT) \ 115 | BIT(IC_RESTART) \ 116 | BIT(IC_STORSTAT) \ 117 ) 118 119 #define SET_IC_INITIAL_MASK(_regs) (_regs)->ints_mask = IC_INITIAL_MASK 120 #define SET_IC_INITIAL_STATE(_regs) (_regs)->ints_state = IC_INITIAL_STATE 121 122 /* I/O interrupt subclasses */ 123 #define IC_IOPENDING ( BIT(IC_IO) ) 124 125 /* External interrupt subclasses in CR 0 */ 126 #define IC_EXT_SCM_CR0 ( BIT(IC_MALFALT) \ 127 | BIT(IC_EMERSIG) \ 128 | BIT(IC_EXTCALL) \ 129 | BIT(IC_TODSYNC) \ 130 | BIT(IC_CLKC) \ 131 | BIT(IC_PTIMER) \ 132 | BIT(IC_SERVSIG) \ 133 | BIT(IC_ITIMER) \ 134 | BIT(IC_INTKEY) \ 135 | BIT(IC_EXTSIG) \ 136 | BIT(IC_ETR) \ 137 ) 138 139 /* External interrupt subclasses */ 140 141 /* 142 * Adds ECPS:VM Vtimer which has no individual 143 * subclass mask in CR0 144 */ 145 #define IC_EXTPENDING ( BIT(IC_MALFALT) \ 146 | BIT(IC_EMERSIG) \ 147 | BIT(IC_EXTCALL) \ 148 | BIT(IC_TODSYNC) \ 149 | BIT(IC_CLKC) \ 150 | BIT(IC_PTIMER) \ 151 | BIT(IC_SERVSIG) \ 152 | BIT(IC_ECPSVTIMER) \ 153 | BIT(IC_ITIMER) \ 154 | BIT(IC_INTKEY) \ 155 | BIT(IC_EXTSIG) \ 156 | BIT(IC_ETR) \ 157 ) 158 159 /* Machine check subclasses */ 160 #define IC_MCKPENDING ( BIT(IC_CHANRPT) \ 161 | BIT(IC_RCVYRPT) \ 162 | BIT(IC_DGRDRPT) \ 163 | BIT(IC_XDMGRPT) \ 164 | BIT(IC_WARNING) \ 165 ) 166 167 /* Not disabled mask */ 168 #define IC_OPEN_MASK ( IC_MCKPENDING \ 169 | IC_EXTPENDING \ 170 | IC_IOPENDING \ 171 ) 172 173 #define IC_PER_MASK ( BIT(IC_PER_SB) \ 174 | BIT(IC_PER_IF) \ 175 | BIT(IC_PER_SA) \ 176 | BIT(IC_PER_GRA) \ 177 | BIT(IC_PER_STURA) \ 178 | BIT(IC_PER_IFNUL) \ 179 ) 180 181 /* SIE & Assist supported events */ 182 #define IC_SIE_INT ( BIT(IC_IO) \ 183 | BIT(IC_CLKC) \ 184 | BIT(IC_PTIMER) \ 185 | BIT(IC_ITIMER) \ 186 ) 187 188 #define IC_CR9_SHIFT 8 189 190 /* Mask bits are ONLY set by the associated cpu thread and 191 * therefore don't have to be serialized. The mask bits 192 * indicate which interrupts the CPU is willing to take at 193 * this time. We set the mask bits below in one fell swoop 194 * to avoid multiple updates to `ints_mask'. 195 */ 196 197 #undef IC_CR0_TO_INTMASK 198 #if defined(FEATURE_ECPSVM) 199 200 #define IC_CR0_TO_INTMASK(_regs) \ 201 ( ( (_regs)->CR(0) & IC_EXT_SCM_CR0) \ 202 | (((_regs)->CR(0) & BIT(IC_ITIMER)) ? BIT(IC_ECPSVTIMER) : 0) ) 203 #else 204 205 #define IC_CR0_TO_INTMASK(_regs) \ 206 ( (_regs)->CR(0) & IC_EXT_SCM_CR0) 207 208 #endif /* FEATURE_ECPSVM */ 209 210 #define IC_MASK(_regs) \ 211 ( ( IC_INITIAL_MASK ) \ 212 | ( ECMODE(&(_regs)->psw) \ 213 ? ( ((_regs)->psw.sysmask & PSW_IOMASK) ? BIT(IC_IO) : 0 ) \ 214 : ( ((_regs)->psw.sysmask & 0xFE) ? BIT(IC_IO) : 0 ) \ 215 ) \ 216 | ( MACHMASK(&(_regs)->psw) ? ((_regs)->CR(14) & IC_MCKPENDING) : 0 ) \ 217 | ( PER_MODE((_regs)) ? ((_regs)->ints_mask & IC_PER_MASK) : 0 ) \ 218 | ( ((_regs)->psw.sysmask & PSW_EXTMASK) ? (IC_CR0_TO_INTMASK((_regs))) : 0 ) \ 219 | ( WAITSTATE(&(_regs)->psw) ? BIT(IC_PSW_WAIT) : 0 ) \ 220 ) 221 222 #define IC_ECMODE_MASK(_regs) \ 223 ( ( IC_INITIAL_MASK ) \ 224 | ( ((_regs)->psw.sysmask & PSW_IOMASK) ? BIT(IC_IO) : 0 ) \ 225 | ( MACHMASK(&(_regs)->psw) ? ((_regs)->CR(14) & IC_MCKPENDING) : 0 ) \ 226 | ( PER_MODE((_regs)) ? ((_regs)->ints_mask & IC_PER_MASK) : 0 ) \ 227 | ( ((_regs)->psw.sysmask & PSW_EXTMASK) ? (IC_CR0_TO_INTMASK((_regs))) : 0 ) \ 228 | ( WAITSTATE(&(_regs)->psw) ? BIT(IC_PSW_WAIT) : 0 ) \ 229 ) 230 231 #define IC_BCMODE_MASK(_regs) \ 232 ( ( IC_INITIAL_MASK ) \ 233 | ( ((_regs)->psw.sysmask & 0xFE) ? BIT(IC_IO) : 0 ) \ 234 | ( MACHMASK(&(_regs)->psw) ? ((_regs)->CR(14) & IC_MCKPENDING) : 0 ) \ 235 | ( PER_MODE((_regs)) ? ((_regs)->ints_mask & IC_PER_MASK) : 0 ) \ 236 | ( ((_regs)->psw.sysmask & PSW_EXTMASK) ? (IC_CR0_TO_INTMASK((_regs))) : 0 ) \ 237 | ( WAITSTATE(&(_regs)->psw) ? BIT(IC_PSW_WAIT) : 0 ) \ 238 ) 239 240 /* Note: if PER mode, invalidate the AIA to force instfetch to be called */ 241 #define SET_IC_ECMODE_MASK(_regs) \ 242 do { \ 243 (_regs)->ints_mask = IC_ECMODE_MASK((_regs)); \ 244 if ( ( (_regs)->permode = PER_MODE((_regs)) ) ) \ 245 INVALIDATE_AIA((_regs)); \ 246 } while (0) 247 248 #define SET_IC_BCMODE_MASK(_regs) \ 249 do { \ 250 (_regs)->ints_mask = IC_BCMODE_MASK((_regs)); \ 251 if ( ( (_regs)->permode = PER_MODE((_regs)) ) ) \ 252 INVALIDATE_AIA((_regs)); \ 253 } while (0) 254 255 #undef SET_IC_MASK 256 #ifdef FEATURE_BCMODE 257 #define SET_IC_MASK(_regs) \ 258 do { \ 259 (_regs)->ints_mask = IC_MASK((_regs)); \ 260 if ( ( (_regs)->permode = PER_MODE((_regs)) ) ) \ 261 INVALIDATE_AIA((_regs)); \ 262 } while (0) 263 #else 264 #define SET_IC_MASK(_regs) SET_IC_ECMODE_MASK(_regs) 265 #endif 266 267 /* 268 * State bits indicate what interrupts are possibly pending 269 * for a CPU. These bits can be set by any thread and therefore 270 * are serialized by the `intlock'. 271 * For PER, the state bits are set when CR9 is loaded and the mask 272 * bits are set when a PER event occurs 273 */ 274 275 #define SET_IC_TRACE \ 276 do { \ 277 int i; \ 278 CPU_BITMAP mask = sysblk.started_mask; \ 279 for (i = 0; mask; i++) { \ 280 if (mask & 1) \ 281 sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT); \ 282 mask >>= 1; \ 283 } \ 284 } while (0) 285 286 #define SET_IC_PER(_regs) \ 287 do { \ 288 (_regs)->ints_state &= (~IC_PER_MASK); \ 289 (_regs)->ints_state |= (((_regs)->CR(9) >> IC_CR9_SHIFT) & IC_PER_MASK); \ 290 (_regs)->ints_mask &= (~IC_PER_MASK | (_regs)->ints_state); \ 291 } while (0) 292 293 /* * * * * * * * * * * * * * 294 * Set state bit to '1' * 295 * * * * * * * * * * * * * */ 296 297 #define ON_IC_INTERRUPT(_regs) \ 298 do { \ 299 (_regs)->ints_state |= BIT(IC_INTERRUPT); \ 300 } while (0) 301 302 #define ON_IC_RESTART(_regs) \ 303 do { \ 304 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_RESTART); \ 305 } while (0) 306 307 #define ON_IC_STORSTAT(_regs) \ 308 do { \ 309 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_STORSTAT); \ 310 } while (0) 311 312 #define ON_IC_IOPENDING \ 313 do { \ 314 int i; CPU_BITMAP mask; \ 315 if ( !(sysblk.ints_state & BIT(IC_IO)) ) { \ 316 sysblk.ints_state |= BIT(IC_IO); \ 317 mask = sysblk.started_mask; \ 318 for (i = 0; mask; i++) { \ 319 if (mask & 1) { \ 320 if ( sysblk.regs[i]->ints_mask & BIT(IC_IO) ) \ 321 sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_IO); \ 322 else \ 323 sysblk.regs[i]->ints_state |= BIT(IC_IO); \ 324 } \ 325 mask >>= 1; \ 326 } \ 327 } \ 328 } while (0) 329 330 #define ON_IC_CHANRPT \ 331 do { \ 332 int i; CPU_BITMAP mask; \ 333 if ( !(sysblk.ints_state & BIT(IC_CHANRPT)) ) { \ 334 sysblk.ints_state |= BIT(IC_CHANRPT); \ 335 mask = sysblk.started_mask; \ 336 for (i = 0; mask; i++) { \ 337 if (mask & 1) { \ 338 if ( sysblk.regs[i]->ints_mask & BIT(IC_CHANRPT) ) \ 339 sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_CHANRPT); \ 340 else \ 341 sysblk.regs[i]->ints_state |= BIT(IC_CHANRPT); \ 342 } \ 343 mask >>= 1; \ 344 } \ 345 } \ 346 } while (0) 347 348 #define ON_IC_INTKEY \ 349 do { \ 350 int i; CPU_BITMAP mask; \ 351 if ( !(sysblk.ints_state & BIT(IC_INTKEY)) ) { \ 352 sysblk.ints_state |= BIT(IC_INTKEY); \ 353 mask = sysblk.started_mask; \ 354 for (i = 0; mask; i++) { \ 355 if (mask & 1) { \ 356 if ( sysblk.regs[i]->ints_mask & BIT(IC_INTKEY) ) \ 357 sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_INTKEY); \ 358 else \ 359 sysblk.regs[i]->ints_state |= BIT(IC_INTKEY); \ 360 } \ 361 mask >>= 1; \ 362 } \ 363 } \ 364 } while (0) 365 366 #define ON_IC_SERVSIG \ 367 do { \ 368 int i; CPU_BITMAP mask; \ 369 if ( !(sysblk.ints_state & BIT(IC_SERVSIG)) ) { \ 370 sysblk.ints_state |= BIT(IC_SERVSIG); \ 371 mask = sysblk.started_mask; \ 372 for (i = 0; mask; i++) { \ 373 if (mask & 1) { \ 374 if ( sysblk.regs[i]->ints_mask & BIT(IC_SERVSIG) ) \ 375 sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_SERVSIG); \ 376 else \ 377 sysblk.regs[i]->ints_state |= BIT(IC_SERVSIG); \ 378 } \ 379 mask >>= 1; \ 380 } \ 381 } \ 382 } while (0) 383 384 #define ON_IC_ITIMER(_regs) \ 385 do { \ 386 if ( (_regs)->ints_mask & BIT(IC_ITIMER) ) \ 387 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_ITIMER); \ 388 else \ 389 (_regs)->ints_state |= BIT(IC_ITIMER); \ 390 } while (0) 391 392 #define ON_IC_PTIMER(_regs) \ 393 do { \ 394 if ( (_regs)->ints_mask & BIT(IC_PTIMER) ) \ 395 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_PTIMER); \ 396 else \ 397 (_regs)->ints_state |= BIT(IC_PTIMER); \ 398 } while (0) 399 400 #define ON_IC_ECPSVTIMER(_regs) \ 401 do { \ 402 if ( (_regs)->ints_mask & BIT(IC_ECPSVTIMER) ) \ 403 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_ECPSVTIMER); \ 404 else \ 405 (_regs)->ints_state |= BIT(IC_ECPSVTIMER); \ 406 } while (0) 407 408 #define ON_IC_CLKC(_regs) \ 409 do { \ 410 if ( (_regs)->ints_mask & BIT(IC_CLKC) ) \ 411 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_CLKC); \ 412 else \ 413 (_regs)->ints_state |= BIT(IC_CLKC); \ 414 } while (0) 415 416 #define ON_IC_EXTCALL(_regs) \ 417 do { \ 418 if ( (_regs)->ints_mask & BIT(IC_EXTCALL) ) \ 419 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_EXTCALL); \ 420 else \ 421 (_regs)->ints_state |= BIT(IC_EXTCALL); \ 422 } while (0) 423 424 #define ON_IC_MALFALT(_regs) \ 425 do { \ 426 if ( (_regs)->ints_mask & BIT(IC_MALFALT) ) \ 427 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_MALFALT); \ 428 else \ 429 (_regs)->ints_state |= BIT(IC_MALFALT); \ 430 } while (0) 431 432 #define ON_IC_EMERSIG(_regs) \ 433 do { \ 434 if ( (_regs)->ints_mask & BIT(IC_EMERSIG) ) \ 435 (_regs)->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_EMERSIG); \ 436 else \ 437 (_regs)->ints_state |= BIT(IC_EMERSIG); \ 438 } while (0) 439 440 /* 441 * When a PER event occurs we set the bit in ints_mask instead of 442 * ints_state; therefore intlock does not need to be held. 443 * The ints_state bits are set when CR9 is loaded. 444 */ 445 446 #define ON_IC_PER_SB(_regs) \ 447 do { \ 448 (_regs)->ints_mask |= BIT(IC_PER_SB); \ 449 } while (0) 450 451 #define ON_IC_PER_IF(_regs) \ 452 do { \ 453 (_regs)->ints_mask |= BIT(IC_PER_IF); \ 454 } while (0) 455 456 #define ON_IC_PER_SA(_regs) \ 457 do { \ 458 (_regs)->ints_mask |= BIT(IC_PER_SA); \ 459 } while (0) 460 461 #define ON_IC_PER_GRA(_regs) \ 462 do { \ 463 (_regs)->ints_mask |= BIT(IC_PER_GRA); \ 464 } while (0) 465 466 #define ON_IC_PER_STURA(_regs) \ 467 do { \ 468 (_regs)->ints_mask |= BIT(IC_PER_STURA); \ 469 } while (0) 470 471 #define ON_IC_PER_IFNUL(_regs) \ 472 do { \ 473 (_regs)->ints_mask |= BIT(IC_PER_IFNUL); \ 474 } while (0) 475 476 477 /* * * * * * * * * * * * * * 478 * Set state bit to '0' * 479 * * * * * * * * * * * * * */ 480 481 #define OFF_IC_INTERRUPT(_regs) \ 482 do { \ 483 (_regs)->ints_state &= ~BIT(IC_INTERRUPT); \ 484 } while (0) 485 486 #define OFF_IC_RESTART(_regs) \ 487 do { \ 488 (_regs)->ints_state &= ~BIT(IC_RESTART); \ 489 } while (0) 490 491 #define OFF_IC_STORSTAT(_regs) \ 492 do { \ 493 (_regs)->ints_state &= ~BIT(IC_STORSTAT); \ 494 } while (0) 495 496 #define OFF_IC_IOPENDING \ 497 do { \ 498 int i; CPU_BITMAP mask; \ 499 if ( sysblk.ints_state & BIT(IC_IO) ) { \ 500 sysblk.ints_state &= ~BIT(IC_IO); \ 501 mask = sysblk.started_mask; \ 502 for (i = 0; mask; i++) { \ 503 if (mask & 1) \ 504 sysblk.regs[i]->ints_state &= ~BIT(IC_IO); \ 505 mask >>= 1; \ 506 } \ 507 } \ 508 } while (0) 509 510 #define OFF_IC_CHANRPT \ 511 do { \ 512 int i; CPU_BITMAP mask; \ 513 if ( sysblk.ints_state & BIT(IC_CHANRPT) ) { \ 514 sysblk.ints_state &= ~BIT(IC_CHANRPT); \ 515 mask = sysblk.started_mask; \ 516 for (i = 0; mask; i++) { \ 517 if (mask & 1) \ 518 sysblk.regs[i]->ints_state &= ~BIT(IC_CHANRPT); \ 519 mask >>= 1; \ 520 } \ 521 } \ 522 } while (0) 523 524 #define OFF_IC_INTKEY \ 525 do { \ 526 int i; CPU_BITMAP mask; \ 527 if ( sysblk.ints_state & BIT(IC_INTKEY) ) { \ 528 sysblk.ints_state &= ~BIT(IC_INTKEY); \ 529 mask = sysblk.started_mask; \ 530 for (i = 0; mask; i++) { \ 531 if (mask & 1) \ 532 sysblk.regs[i]->ints_state &= ~BIT(IC_INTKEY); \ 533 mask >>= 1; \ 534 } \ 535 } \ 536 } while (0) 537 538 #define OFF_IC_SERVSIG \ 539 do { \ 540 int i; CPU_BITMAP mask; \ 541 if ( sysblk.ints_state & BIT(IC_SERVSIG) ) { \ 542 sysblk.ints_state &= ~BIT(IC_SERVSIG); \ 543 mask = sysblk.started_mask; \ 544 for (i = 0; mask; i++) { \ 545 if (mask & 1) \ 546 sysblk.regs[i]->ints_state &= ~BIT(IC_SERVSIG); \ 547 mask >>= 1; \ 548 } \ 549 } \ 550 } while (0) 551 552 #define OFF_IC_ITIMER(_regs) \ 553 do { \ 554 (_regs)->ints_state &= ~BIT(IC_ITIMER); \ 555 } while (0) 556 557 #define OFF_IC_PTIMER(_regs) \ 558 do { \ 559 (_regs)->ints_state &= ~BIT(IC_PTIMER); \ 560 } while (0) 561 562 #define OFF_IC_ECPSVTIMER(_regs) \ 563 do { \ 564 (_regs)->ints_state &= ~BIT(IC_ECPSVTIMER); \ 565 } while (0) 566 567 #define OFF_IC_CLKC(_regs) \ 568 do { \ 569 (_regs)->ints_state &= ~BIT(IC_CLKC); \ 570 } while (0) 571 572 #define OFF_IC_EXTCALL(_regs) \ 573 do { \ 574 (_regs)->ints_state &= ~BIT(IC_EXTCALL); \ 575 } while (0) 576 577 #define OFF_IC_MALFALT(_regs) \ 578 do { \ 579 (_regs)->ints_state &= ~BIT(IC_MALFALT); \ 580 } while (0) 581 582 #define OFF_IC_EMERSIG(_regs) \ 583 do { \ 584 (_regs)->ints_state &= ~BIT(IC_EMERSIG); \ 585 } while (0) 586 587 #define OFF_IC_PER(_regs) \ 588 do { \ 589 (_regs)->ints_mask &= ~IC_PER_MASK; \ 590 } while (0) 591 592 #define OFF_IC_PER_SB(_regs) \ 593 do { \ 594 (_regs)->ints_mask &= ~BIT(IC_PER_SB); \ 595 } while (0) 596 597 #define OFF_IC_PER_IF(_regs) \ 598 do { \ 599 (_regs)->ints_mask &= ~BIT(IC_PER_IF); \ 600 } while (0) 601 602 #define OFF_IC_PER_SA(_regs) \ 603 do { \ 604 (_regs)->ints_mask &= ~BIT(IC_PER_SA); \ 605 } while (0) 606 607 #define OFF_IC_PER_GRA(_regs) \ 608 do { \ 609 (_regs)->ints_mask &= ~BIT(IC_PER_GRA); \ 610 } while (0) 611 612 #define OFF_IC_PER_STURA(_regs) \ 613 do { \ 614 (_regs)->ints_mask &= ~BIT(IC_PER_STURA); \ 615 } while (0) 616 617 #define OFF_IC_PER_IFNUL(_regs) \ 618 do { \ 619 (_regs)->ints_mask &= ~BIT(IC_PER_IFNUL); \ 620 } while (0) 621 622 623 /* * * * * * * * * * * * * * 624 * Test interrupt state * 625 * * * * * * * * * * * * * */ 626 627 #define IS_IC_INTERRUPT(_regs) ( (_regs)->ints_state & BIT(IC_INTERRUPT) ) 628 #define IS_IC_RESTART(_regs) ( (_regs)->ints_state & BIT(IC_RESTART) ) 629 #define IS_IC_STORSTAT(_regs) ( (_regs)->ints_state & BIT(IC_STORSTAT) ) 630 #define IS_IC_IOPENDING ( sysblk.ints_state & BIT(IC_IO) ) 631 #define IS_IC_MCKPENDING(_regs) ( (_regs)->ints_state & IC_MCKPENDING ) 632 #define IS_IC_CHANRPT ( sysblk.ints_state & BIT(IC_CHANRPT) ) 633 #define IS_IC_INTKEY ( sysblk.ints_state & BIT(IC_INTKEY) ) 634 #define IS_IC_SERVSIG ( sysblk.ints_state & BIT(IC_SERVSIG) ) 635 #define IS_IC_ITIMER(_regs) ( (_regs)->ints_state & BIT(IC_ITIMER) ) 636 #define IS_IC_PTIMER(_regs) ( (_regs)->ints_state & BIT(IC_PTIMER) ) 637 #define IS_IC_ECPSVTIMER(_regs) ( (_regs)->ints_state & BIT(IC_ECPSVTIMER)) 638 #define IS_IC_CLKC(_regs) ( (_regs)->ints_state & BIT(IC_CLKC) ) 639 #define IS_IC_EXTCALL(_regs) ( (_regs)->ints_state & BIT(IC_EXTCALL) ) 640 #define IS_IC_MALFALT(_regs) ( (_regs)->ints_state & BIT(IC_MALFALT) ) 641 #define IS_IC_EMERSIG(_regs) ( (_regs)->ints_state & BIT(IC_EMERSIG) ) 642 #define IS_IC_PER(_regs) ( (_regs)->ints_mask & IC_PER_MASK ) 643 #define IS_IC_PER_SB(_regs) ( (_regs)->ints_mask & BIT(IC_PER_SB) ) 644 #define IS_IC_PER_IF(_regs) ( (_regs)->ints_mask & BIT(IC_PER_IF) ) 645 #define IS_IC_PER_SA(_regs) ( (_regs)->ints_mask & BIT(IC_PER_SA) ) 646 #define IS_IC_PER_GRA(_regs) ( (_regs)->ints_mask & BIT(IC_PER_GRA) ) 647 #define IS_IC_PER_STURA(_regs) ( (_regs)->ints_mask & BIT(IC_PER_STURA) ) 648 #define IS_IC_PER_IFNUL(_regs) ( (_regs)->ints_mask & BIT(IC_PER_IFNUL) ) 649 650 651 /* * * * * * * * * * * * * * 652 * Disabled wait check * 653 * * * * * * * * * * * * * */ 654 655 #define IS_IC_DISABLED_WAIT_PSW(_regs) \ 656 ( ((_regs)->ints_mask & IC_OPEN_MASK) == 0 ) 657 658 659 /* * * * * * * * * * * * * * 660 * Test PER mask bits * 661 * * * * * * * * * * * * * */ 662 663 #define EN_IC_PER(_regs) unlikely( (_regs)->permode ) 664 #define EN_IC_PER_SB(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_SB)) ) 665 #define EN_IC_PER_IF(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_IF)) ) 666 #define EN_IC_PER_SA(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_SA)) ) 667 #define EN_IC_PER_GRA(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_GRA)) ) 668 #define EN_IC_PER_STURA(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_STURA)) ) 669 #define EN_IC_PER_IFNUL(_regs) ( EN_IC_PER(_regs) && ((_regs)->ints_state & BIT(IC_PER_IFNUL)) ) 670 671 672 /* * * * * * * * * * * * * * * * * * * * * * * * * 673 * Check for specific enabled pending interrupt * 674 * * * * * * * * * * * * * * * * * * * * * * * * */ 675 676 #define OPEN_IC_MCKPENDING(_regs) \ 677 ( (_regs)->ints_state & (_regs)->ints_mask & IC_MCKPENDING ) 678 679 #define OPEN_IC_IOPENDING(_regs) \ 680 ( (_regs)->ints_state & (_regs)->ints_mask & IC_IOPENDING ) 681 682 #define OPEN_IC_CHANRPT(_regs) \ 683 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_CHANRPT) ) 684 685 #define OPEN_IC_EXTPENDING(_regs) \ 686 ( (_regs)->ints_state & (_regs)->ints_mask & IC_EXTPENDING ) 687 688 #define OPEN_IC_ITIMER(_regs) \ 689 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_ITIMER) ) 690 691 #define OPEN_IC_PTIMER(_regs) \ 692 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PTIMER) ) 693 694 #define OPEN_IC_ECPSVTIMER(_regs) \ 695 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_ECPSVTIMER) ) 696 697 #define OPEN_IC_CLKC(_regs) \ 698 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_CLKC) ) 699 700 #define OPEN_IC_INTKEY(_regs) \ 701 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_INTKEY) ) 702 703 #define OPEN_IC_SERVSIG(_regs) \ 704 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_SERVSIG) ) 705 706 #define OPEN_IC_EXTCALL(_regs) \ 707 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_EXTCALL) ) 708 709 #define OPEN_IC_MALFALT(_regs) \ 710 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_MALFALT) ) 711 712 #define OPEN_IC_EMERSIG(_regs) \ 713 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_EMERSIG) ) 714 715 #define OPEN_IC_PER(_regs) \ 716 ( (_regs)->ints_state & (_regs)->ints_mask & IC_PER_MASK ) 717 #define OPEN_IC_PER_SB(_regs) \ 718 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_SB) ) 719 #define OPEN_IC_PER_IF(_regs) \ 720 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_IF) ) 721 #define OPEN_IC_PER_SA(_regs) \ 722 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_SA) ) 723 #define OPEN_IC_PER_GRA(_regs) \ 724 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_GRA) ) 725 #define OPEN_IC_PER_STURA(_regs) \ 726 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_STURA) ) 727 #define OPEN_IC_PER_IFNUL(_regs) \ 728 ( (_regs)->ints_state & (_regs)->ints_mask & BIT(IC_PER_IFNUL) ) 729 730 /* * * * * * * * * * * * * * * * * * * * * * * * * 731 * Check for general enabled pending interrupt * 732 * * * * * * * * * * * * * * * * * * * * * * * * */ 733 734 #define IC_INTERRUPT_CPU(_regs) \ 735 ( (_regs)->ints_state & (_regs)->ints_mask ) 736 #define INTERRUPT_PENDING(_regs) IC_INTERRUPT_CPU((_regs)) 737 738 #define SIE_IC_INTERRUPT_CPU(_regs) \ 739 (((_regs)->ints_state|((_regs)->hostregs->ints_state&IC_SIE_INT)) & (_regs)->ints_mask) 740 #define SIE_INTERRUPT_PENDING(_regs) SIE_IC_INTERRUPT_CPU((_regs)) 741