1 /** @file 2 3 Copyright (c) 2016 - 2017, Socionext Inc. All rights reserved.<BR> 4 Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef OGMA_API_H 11 #define OGMA_API_H 12 13 #include "ogma_version.h" 14 #include "netsec_for_uefi/ogma_config.h" 15 #include "netsec_for_uefi/netsec_sdk/include/ogma_basic_type.h" 16 #include "netsec_for_uefi/pfdep.h" 17 /** 18 * Check configuration macro settings. 19 */ 20 #ifdef OGMA_CONFIG_CLK_HZ 21 #if ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) 22 #error "OGMA_CONFIG_CLK_HZ is not appropriate." 23 #endif /* ( (OGMA_CONFIG_CLK_HZ < 0x200000) || (OGMA_CONFIG_CLK_HZ > 0x10000000) ) */ 24 #else /* ! OGMA_CONFIG_CLK_HZ */ 25 #error "OGMA_CONFIG_CLK_HZ is not given." 26 #endif /* OGMA_CONFIG_CLK_HZ */ 27 28 #ifndef OGMA_CONFIG_GMAC_CLK_HZ 29 #define OGMA_CONFIG_GMAC_CLK_HZ OGMA_CONFIG_CLK_HZ 30 #endif 31 32 /** 33 * Number of hardware limits 34 */ 35 36 37 /** 38 * Number of Common Descriptor ring id 39 */ 40 #define OGMA_DESC_RING_ID_NRM_TX 0 41 #define OGMA_DESC_RING_ID_NRM_RX 1 42 43 #define OGMA_DESC_RING_ID_GMAC 15 44 #define OGMA_DESC_RING_ID_MAX 1 45 46 /** 47 * Numbre of TCP Segmentation length limits 48 */ 49 #define OGMA_TCP_SEG_LEN_MAX 1460 50 #define OGMA_TCP_JUMBO_SEG_LEN_MAX 8960 51 52 /** 53 * Number of ER check result for received packet 54 */ 55 #define OGMA_RX_ER_RESULT_NG 0x1 56 #define OGMA_RX_ER_RESULT_OK 0x0 57 58 /** 59 * Number of checksum calculation result for received packet 60 */ 61 #define OGMA_RX_CKSUM_RESULT_OK 0x1 62 #define OGMA_RX_CKSUM_RESULT_NG 0x2 63 #define OGMA_RX_CKSUM_RESULT_NOTAVAIL 0x0 64 65 /** 66 * Number of ErrorCode for received packet 67 */ 68 #define OGMA_RX_ERRCODE_HEADER_INCOMLETE_ERR 0x2 69 #define OGMA_RX_ERRCODE_IP_HEADER_ERR 0x1 70 #define OGMA_RX_ERRCODE_NONE 0x0 71 72 /** 73 * Number of top interrupt enable register bit field 74 */ 75 #define OGMA_TOP_IRQ_REG_ME_START (1UL << 20) 76 #define OGMA_TOP_IRQ_REG_MAC (1UL << 19) 77 #define OGMA_TOP_IRQ_REG_PKT (1UL << 18) 78 #define OGMA_TOP_IRQ_REG_BOOTCODE_TX (1UL << 5) 79 #define OGMA_TOP_IRQ_REG_NRM_RX (1UL << 1) 80 #define OGMA_TOP_IRQ_REG_NRM_TX (1UL << 0) 81 82 83 /** 84 * Number of top channel enable register bit field 85 */ 86 #define OGMA_CH_IRQ_REG_EMPTY (1UL << 17) 87 #define OGMA_CH_IRQ_REG_ERR (1UL << 16) 88 #define OGMA_CH_IRQ_REG_PKT_CNT (1UL << 15) 89 #define OGMA_CH_IRQ_REG_TIMEUP (1UL << 14) 90 #define OGMA_CH_IRQ_REG_RCV (OGMA_CH_IRQ_REG_PKT_CNT | OGMA_CH_IRQ_REG_TIMEUP) 91 92 /** 93 * Number of top channel enable register bit field for F_NETSEC_C 94 */ 95 #define OGMA_CH_IRQ_REG_TX_DONE (1UL << 15) 96 #define OGMA_CH_IRQ_REG_SND (OGMA_CH_IRQ_REG_TX_DONE | OGMA_CH_IRQ_REG_TIMEUP) 97 98 99 /** 100 * Number of packet interrupt enable register bit field 101 */ 102 #define OGMA_PKT_IRQ_MAC_ER (1UL << 5) 103 #define OGMA_PKT_IRQ_JUMBO_ER (1UL << 4) 104 #define OGMA_PKT_IRQ_CHKSUM_ER (1UL << 3) 105 #define OGMA_PKT_IRQ_HD_INCOMPLETE (1UL << 2) 106 #define OGMA_PKT_IRQ_HD_ER (1UL << 1) 107 #define OGMA_PKT_IRQ_DRP_NO_MATCH (1UL << 0) 108 109 110 /** 111 * Number of mac irq enable register bit field 112 */ 113 #define OGMA_MAC_IRQ_INT_PMT (1UL << 31) 114 #define OGMA_MAC_IRQ_INT_SBD (1UL << 30) 115 #define OGMA_MAC_IRQ_INT_LPI (1UL << 29) 116 #define OGMA_MAC_IRQ_INT_MAC_TX_RX_INFO_INT (1UL << 27) 117 #define OGMA_MAC_IRQ_INT_LPI_TX_ENTRY (1UL << 26) 118 #define OGMA_MAC_IRQ_INT_LPI_RX_ENTRY (1UL << 25) 119 #define OGMA_MAC_IRQ_INT_LPI_TX_EXIT (1UL << 24) 120 #define OGMA_MAC_IRQ_INT_LPI_RX_EXIT (1UL << 23) 121 122 123 /** 124 * Number of SR IER register bit field 125 */ 126 #define OGMA_GMAC_INT_SBD_IRQ_SR_GLPII (1U << 30) 127 #define OGMA_GMAC_INT_SBD_IRQ_SR_TTI (1U << 29) 128 #define OGMA_GMAC_INT_SBD_IRQ_SR_GPI (1U << 28) 129 #define OGMA_GMAC_INT_SBD_IRQ_SR_GMI (1U << 27) 130 #define OGMA_GMAC_INT_SBD_IRQ_SR_GLI (1U << 26) 131 #define OGMA_GMAC_INT_SBD_IRQ_SR_NIS (1U << 16) 132 #define OGMA_GMAC_INT_SBD_IRQ_SR_AIS (1U << 15) 133 #define OGMA_GMAC_INT_SBD_IRQ_SR_ERI (1U << 14) 134 #define OGMA_GMAC_INT_SBD_IRQ_SR_FBI (1U << 13) 135 #define OGMA_GMAC_INT_SBD_IRQ_SR_ETI (1U << 10) 136 #define OGMA_GMAC_INT_SBD_IRQ_SR_RWT (1U << 9) 137 #define OGMA_GMAC_INT_SBD_IRQ_SR_RPS (1U << 8) 138 #define OGMA_GMAC_INT_SBD_IRQ_SR_RU (1U << 7) 139 #define OGMA_GMAC_INT_SBD_IRQ_SR_RI (1U << 6) 140 #define OGMA_GMAC_INT_SBD_IRQ_SR_UNF (1U << 5) 141 #define OGMA_GMAC_INT_SBD_IRQ_SR_OVF (1U << 4) 142 #define OGMA_GMAC_INT_SBD_IRQ_SR_TJT (1U << 3) 143 #define OGMA_GMAC_INT_SBD_IRQ_SR_TU (1U << 2) 144 #define OGMA_GMAC_INT_SBD_IRQ_SR_TPS (1U << 1) 145 #define OGMA_GMAC_INT_SBD_IRQ_SR_TI (1U << 0) 146 #define OGMA_GMAC_INT_SBD_IRQ_SR_WC_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \ 147 OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \ 148 OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \ 149 OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \ 150 OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \ 151 OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \ 152 OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \ 153 OGMA_GMAC_INT_SBD_IRQ_SR_RU | \ 154 OGMA_GMAC_INT_SBD_IRQ_SR_RI | \ 155 OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \ 156 OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \ 157 OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \ 158 OGMA_GMAC_INT_SBD_IRQ_SR_TU | \ 159 OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \ 160 OGMA_GMAC_INT_SBD_IRQ_SR_TI) 161 162 #define OGMA_GMAC_INT_SBD_IRQ_SR_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_GLPII | \ 163 OGMA_GMAC_INT_SBD_IRQ_SR_TTI | \ 164 OGMA_GMAC_INT_SBD_IRQ_SR_GPI | \ 165 OGMA_GMAC_INT_SBD_IRQ_SR_GMI | \ 166 OGMA_GMAC_INT_SBD_IRQ_SR_GLI | \ 167 OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \ 168 OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \ 169 OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \ 170 OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \ 171 OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \ 172 OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \ 173 OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \ 174 OGMA_GMAC_INT_SBD_IRQ_SR_RU | \ 175 OGMA_GMAC_INT_SBD_IRQ_SR_RI | \ 176 OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \ 177 OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \ 178 OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \ 179 OGMA_GMAC_INT_SBD_IRQ_SR_TU | \ 180 OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \ 181 OGMA_GMAC_INT_SBD_IRQ_SR_TI) 182 183 #define OGMA_GMAC_INT_SBD_IRQ_IER_ALL ( OGMA_GMAC_INT_SBD_IRQ_SR_NIS | \ 184 OGMA_GMAC_INT_SBD_IRQ_SR_AIS | \ 185 OGMA_GMAC_INT_SBD_IRQ_SR_ERI | \ 186 OGMA_GMAC_INT_SBD_IRQ_SR_FBI | \ 187 OGMA_GMAC_INT_SBD_IRQ_SR_ETI | \ 188 OGMA_GMAC_INT_SBD_IRQ_SR_RWT | \ 189 OGMA_GMAC_INT_SBD_IRQ_SR_RPS | \ 190 OGMA_GMAC_INT_SBD_IRQ_SR_RU | \ 191 OGMA_GMAC_INT_SBD_IRQ_SR_RI | \ 192 OGMA_GMAC_INT_SBD_IRQ_SR_UNF | \ 193 OGMA_GMAC_INT_SBD_IRQ_SR_OVF | \ 194 OGMA_GMAC_INT_SBD_IRQ_SR_TJT | \ 195 OGMA_GMAC_INT_SBD_IRQ_SR_TU | \ 196 OGMA_GMAC_INT_SBD_IRQ_SR_TPS | \ 197 OGMA_GMAC_INT_SBD_IRQ_SR_TI) 198 199 /** 200 * Number of ISR IMR register bit field 201 */ 202 #define OGMA_GMAC_INT_SBD_IRQ_ISR_LPII (1U << 10) 203 #define OGMA_GMAC_INT_SBD_IRQ_ISR_TSI (1U << 9) 204 #define OGMA_GMAC_INT_SBD_IRQ_ISR_COI (1U << 7) 205 #define OGMA_GMAC_INT_SBD_IRQ_ISR_TI (1U << 6) 206 #define OGMA_GMAC_INT_SBD_IRQ_ISR_RI (1U << 5) 207 #define OGMA_GMAC_INT_SBD_IRQ_ISR_MI (1U << 4) 208 #define OGMA_GMAC_INT_SBD_IRQ_ISR_PI (1U << 3) 209 #define OGMA_GMAC_INT_SBD_IRQ_ISR_RGI (1U << 0) 210 #define OGMA_GMAC_INT_SBD_IRQ_ISR_ALL ( OGMA_GMAC_INT_SBD_IRQ_ISR_LPII | \ 211 OGMA_GMAC_INT_SBD_IRQ_ISR_TSI | \ 212 OGMA_GMAC_INT_SBD_IRQ_ISR_COI | \ 213 OGMA_GMAC_INT_SBD_IRQ_ISR_TI | \ 214 OGMA_GMAC_INT_SBD_IRQ_ISR_RI | \ 215 OGMA_GMAC_INT_SBD_IRQ_ISR_MI | \ 216 OGMA_GMAC_INT_SBD_IRQ_ISR_PI | \ 217 OGMA_GMAC_INT_SBD_IRQ_ISR_RGI) 218 219 /** 220 * Number of LPICSR register bit field 221 */ 222 #define OGMA_GMAC_LPICSR_REG_LPITXA (1U << 19) 223 #define OGMA_GMAC_LPICSR_REG_PLSEN (1U << 18) 224 #define OGMA_GMAC_LPICSR_REG_PLS (1U << 17) 225 #define OGMA_GMAC_LPICSR_REG_LPIEN (1U << 16) 226 #define OGMA_GMAC_LPICSR_REG_RLPIST (1U << 9) 227 #define OGMA_GMAC_LPICSR_REG_TLPIST (1U << 8) 228 #define OGMA_GMAC_LPICSR_REG_RLPIEX (1U << 3) 229 #define OGMA_GMAC_LPICSR_REG_RLPIEN (1U << 2) 230 #define OGMA_GMAC_LPICSR_REG_TLPIEX (1U << 1) 231 #define OGMA_GMAC_LPICSR_REG_TLPIEN (1U << 0) 232 233 /** 234 * Number of RGSR register bit field 235 */ 236 #define OGMA_GMAC_RGSR_REG_LS (1U << 3) 237 #define OGMA_GMAC_RGSR_REG_LSP (1U << 1) 238 #define OGMA_GMAC_RGSR_REG_LM (1U << 0) 239 240 /** 241 * Number of various limits 242 */ 243 #define OGMA_DESC_ENTRY_NUM_MIN 2 244 #define OGMA_DESC_ENTRY_NUM_MAX 2047 245 #define OGMA_INT_PKTCNT_MAX 2047 246 #define OGMA_L4_MIN_LEN_MAX 64 247 248 /** 249 * Number of ogma phy interface setting 250 */ 251 #define OGMA_PHY_INTERFACE_GMII 0 252 #define OGMA_PHY_INTERFACE_RGMII 1 253 #define OGMA_PHY_INTERFACE_RMII 4 254 255 /** 256 * Number of ogma link speed setting 257 */ 258 #define OGMA_PHY_LINK_SPEED_1G 0 259 #define OGMA_PHY_LINK_SPEED_100M 1U 260 #define OGMA_PHY_LINK_SPEED_10M 2U 261 #define OGMA_PHY_LINK_SPEED_100M_OR_10M 3U 262 263 /** 264 * Number of flow control limits 265 */ 266 #define OGMA_FLOW_CTRL_START_THRESHOLD_MAX 95 267 #define OGMA_FLOW_CTRL_STOP_THRESHOLD_MAX 95 268 #define OGMA_FLOW_CTRL_PAUSE_TIME_MIN 5 269 270 enum ogma_err_e{ 271 OGMA_ERR_OK = 0, 272 OGMA_ERR_PARAM, 273 OGMA_ERR_ALLOC, 274 OGMA_ERR_BUSY, 275 OGMA_ERR_RANGE, 276 OGMA_ERR_DATA, 277 OGMA_ERR_NOTAVAIL, 278 OGMA_ERR_INTERRUPT, 279 OGMA_ERR_AGAIN, 280 OGMA_ERR_INVALID, 281 }; 282 283 typedef void *ogma_handle_t; 284 typedef struct ogma_param_s ogma_param_t; 285 typedef struct ogma_pkt_ctrl_param_s ogma_pkt_ctrl_param_t; 286 typedef struct ogma_desc_ring_param_s ogma_desc_ring_param_t; 287 typedef enum ogma_err_e ogma_err_t; 288 typedef ogma_uint8 ogma_desc_ring_id_t; 289 typedef struct ogma_tx_pkt_ctrl_s ogma_tx_pkt_ctrl_t; 290 typedef struct ogma_rx_pkt_info_s ogma_rx_pkt_info_t; 291 typedef struct ogma_frag_info_s ogma_frag_info_t; 292 typedef struct ogma_gmac_config_s ogma_gmac_config_t; 293 typedef struct ogma_gmac_mode_s ogma_gmac_mode_t; 294 295 struct ogma_gmac_config_s{ 296 ogma_uint8 phy_interface; 297 }; 298 299 struct ogma_pkt_ctrl_param_s{ 300 ogma_uint log_chksum_er_flag:1; 301 ogma_uint log_hd_imcomplete_flag:1; 302 ogma_uint log_hd_er_flag:1; 303 ogma_uint drp_no_match_flag:1; 304 }; 305 306 struct ogma_desc_ring_param_s{ 307 ogma_uint valid_flag:1; 308 ogma_uint little_endian_flag:1; 309 ogma_uint tmr_mode_flag:1; 310 ogma_uint16 entry_num; 311 }; 312 313 struct ogma_param_s{ 314 315 ogma_uint use_gmac_flag:1; 316 ogma_uint use_jumbo_pkt_flag:1; 317 ogma_pkt_ctrl_param_t pkt_ctrl_param; 318 ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1]; 319 ogma_gmac_config_t gmac_config; 320 ogma_uint8 mac_addr[6]; 321 ogma_uint8 phy_addr; 322 }; 323 324 struct ogma_tx_pkt_ctrl_s{ 325 ogma_uint pass_through_flag:1; 326 ogma_uint cksum_offload_flag:1; 327 ogma_uint tcp_seg_offload_flag:1; 328 ogma_desc_ring_id_t target_desc_ring_id; 329 ogma_uint16 tcp_seg_len; 330 }; 331 332 struct ogma_rx_pkt_info_s{ 333 ogma_uint fragmented_flag:1; 334 ogma_uint err_flag:1; 335 ogma_uint rx_cksum_result:2; 336 ogma_uint8 err_code; 337 }; 338 339 struct ogma_frag_info_s{ 340 pfdep_phys_addr_t phys_addr; 341 void *addr; 342 ogma_uint32 len; 343 }; 344 345 struct ogma_gmac_mode_s{ 346 ogma_uint half_duplex_flag:1; 347 ogma_uint flow_ctrl_enable_flag:1; 348 ogma_uint8 link_speed; 349 ogma_uint16 flow_ctrl_start_threshold; 350 ogma_uint16 flow_ctrl_stop_threshold; 351 ogma_uint16 pause_time; 352 }; 353 354 #ifdef OGMA_CONFIG_REC_STAT 355 typedef struct ogma_stat_info_s { 356 ogma_uint16 current_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1]; 357 ogma_uint16 max_busy_entry_num[OGMA_DESC_RING_ID_MAX + 1]; 358 } ogma_stat_info_t; 359 #endif /* OGMA_CONFIG_REC_STAT */ 360 361 typedef struct ogma_gmac_int_sbd_regs_s{ 362 ogma_uint32 base; 363 ogma_uint32 extended; 364 } ogma_gmac_int_sbd_regs_t; 365 366 typedef struct ogma_phy_link_status_s{ 367 ogma_uint up_flag:1; 368 ogma_uint auto_nego_enable_flag:1; 369 ogma_uint auto_nego_complete_flag:1; 370 ogma_uint half_duplex_flag:1; 371 ogma_uint latched_link_down_flag:1; 372 ogma_uint lpi_capable_flag:1; 373 ogma_uint8 link_speed; 374 } ogma_phy_link_status_t; 375 376 /************************** 377 *************************** 378 ***************************/ 379 380 ogma_err_t ogma_init ( 381 void *base_addr, 382 pfdep_dev_handle_t dev_handle, 383 const ogma_param_t *param_p, 384 const void *dma_hm_mc_addr, 385 ogma_uint32 dma_hm_mc_len, 386 const void *dma_mh_mc_addr, 387 ogma_uint32 dma_mh_mc_len, 388 const void *pktc_mc_addr, 389 ogma_uint32 pktc_mc_len, 390 ogma_handle_t *ogma_handle_p 391 ); 392 393 void ogma_terminate ( 394 ogma_handle_t ogma_handle 395 ); 396 397 ogma_err_t ogma_start_gmac ( 398 ogma_handle_t ogma_handle, 399 ogma_bool rx_flag, 400 ogma_bool tx_flag 401 ); 402 403 ogma_err_t ogma_stop_gmac ( 404 ogma_handle_t ogma_handle, 405 ogma_bool rx_flag, 406 ogma_bool tx_flag 407 ); 408 409 ogma_err_t ogma_set_gmac_mode ( 410 ogma_handle_t ogma_handle, 411 const ogma_gmac_mode_t *gmac_mode_p 412 ); 413 414 void ogma_set_phy_reg ( 415 ogma_handle_t ogma_handle, 416 ogma_uint8 reg_addr, 417 ogma_uint16 value 418 ); 419 420 ogma_uint16 ogma_get_phy_reg ( 421 ogma_handle_t ogma_handle, 422 ogma_uint8 reg_addr 423 ); 424 425 ogma_err_t ogma_get_gmac_status ( 426 ogma_handle_t ogma_handle, 427 ogma_bool *valid_flag_p, 428 ogma_gmac_mode_t *gmac_mode_p, 429 ogma_bool *rx_running_flag_p, 430 ogma_bool *tx_running_flag_p 431 ); 432 433 ogma_uint32 ogma_get_top_irq_enable ( 434 ogma_handle_t ogma_handle 435 ); 436 437 ogma_uint32 ogma_get_top_irq_status ( 438 ogma_handle_t ogma_handle, 439 ogma_bool mask_flag 440 ); 441 442 #define ogma_get_top_irq_status_non_clear(ogma_handle,mask_flag) \ 443 ogma_get_top_irq_status(ogma_handle,mask_flag) 444 445 ogma_err_t ogma_clear_top_irq_status ( 446 ogma_handle_t ogma_handle, 447 ogma_uint32 value 448 ); 449 450 ogma_uint32 ogma_get_desc_ring_irq_enable ( 451 ogma_handle_t ogma_handle, 452 ogma_desc_ring_id_t ring_id 453 ); 454 455 ogma_uint32 ogma_get_desc_ring_irq_status ( 456 ogma_handle_t ogma_handle, 457 ogma_desc_ring_id_t ring_id, 458 ogma_bool mask_flag 459 ); 460 461 #define ogma_get_desc_ring_irq_status_non_clear(ogma_handle,ring_id,mask_flag) \ 462 ogma_get_desc_ring_irq_status(ogma_handle,ring_id,mask_flag) 463 464 465 466 ogma_err_t ogma_clear_desc_ring_irq_status ( 467 ogma_handle_t ogma_handle, 468 ogma_desc_ring_id_t ring_id, 469 ogma_uint32 value 470 ); 471 472 ogma_uint32 ogma_get_pkt_irq_enable ( 473 ogma_handle_t ogma_handle 474 ); 475 476 ogma_uint32 ogma_get_pkt_irq_status ( 477 ogma_handle_t ogma_handle, 478 ogma_bool mask_flag 479 ); 480 481 #define ogma_get_pkt_irq_status_non_clear(ogma_handle,mask_flag) \ 482 ogma_get_pkt_irq_status(ogma_handle,mask_flag) 483 484 485 ogma_err_t ogma_clear_pkt_irq_status ( 486 ogma_handle_t ogma_handle, 487 ogma_uint32 value 488 ); 489 490 /* ogma_desc_ring_access.c */ 491 ogma_err_t ogma_start_desc_ring ( 492 ogma_handle_t ogma_handle, 493 ogma_desc_ring_id_t ring_id 494 ); 495 496 ogma_err_t ogma_stop_desc_ring ( 497 ogma_handle_t ogma_handle, 498 ogma_desc_ring_id_t ring_id 499 ); 500 501 ogma_uint16 ogma_get_rx_num ( 502 ogma_handle_t ogma_handle, 503 ogma_desc_ring_id_t ring_id 504 ); 505 506 ogma_uint16 ogma_get_tx_avail_num ( 507 ogma_handle_t ogma_handle, 508 ogma_desc_ring_id_t ring_id 509 ); 510 511 ogma_err_t ogma_clean_tx_desc_ring( 512 ogma_handle_t ogma_handle, 513 ogma_desc_ring_id_t ring_id 514 ); 515 516 ogma_err_t ogma_clean_rx_desc_ring( 517 ogma_handle_t ogma_handle, 518 ogma_desc_ring_id_t ring_id 519 ); 520 521 ogma_err_t ogma_set_tx_pkt_data ( 522 ogma_handle_t ogma_handle, 523 ogma_desc_ring_id_t ring_id, 524 const ogma_tx_pkt_ctrl_t *tx_pkt_ctrl_p, 525 ogma_uint8 scat_num, 526 const ogma_frag_info_t *scat_info_p, 527 pfdep_pkt_handle_t pkt_handle 528 ); 529 530 ogma_err_t ogma_get_rx_pkt_data ( 531 ogma_handle_t ogma_handle, 532 ogma_desc_ring_id_t ring_id, 533 ogma_rx_pkt_info_t *rx_pkt_info_p, 534 ogma_frag_info_t *frag_info_p, 535 ogma_uint16 *len_p, 536 pfdep_pkt_handle_t *pkt_handle_p 537 ); 538 539 ogma_err_t ogma_enable_top_irq ( 540 ogma_handle_t ogma_handle, 541 ogma_uint32 irq_factor 542 ); 543 544 ogma_err_t ogma_disable_top_irq ( 545 ogma_handle_t ogma_handle, 546 ogma_uint32 irq_factor 547 ); 548 549 ogma_err_t ogma_enable_desc_ring_irq ( 550 ogma_handle_t ogma_handle, 551 ogma_desc_ring_id_t ring_id, 552 ogma_uint32 irq_factor 553 ); 554 555 ogma_err_t ogma_disable_desc_ring_irq ( 556 ogma_handle_t ogma_handle, 557 ogma_desc_ring_id_t ring_id, 558 ogma_uint32 irq_factor 559 ); 560 561 ogma_err_t ogma_enable_pkt_irq ( 562 ogma_handle_t ogma_handle, 563 ogma_uint32 irq_factor 564 ); 565 566 ogma_err_t ogma_disable_pkt_irq ( 567 ogma_handle_t ogma_handle, 568 ogma_uint32 irq_factor 569 ); 570 571 ogma_uint32 ogma_get_hw_ver ( 572 ogma_handle_t ogma_handle 573 ); 574 575 ogma_uint32 ogma_get_mcr_ver ( 576 ogma_handle_t ogma_handle 577 ); 578 579 /** 580 * Set up IRQ coalesce parameters. 581 * 582 * [Note] 583 * - This is a tentative implementation. 584 * Not tested enough. Use with care. 585 * 586 * - Call this function after every invocation of ogma_start_desc_ring() 587 * because ogma_start_desc_ring() resets IRQ coalesce settings. 588 * 589 */ 590 ogma_err_t ogma_set_irq_coalesce_param ( 591 ogma_handle_t ogma_handle, 592 ogma_desc_ring_id_t ring_id, 593 ogma_uint16 int_pktcnt, 594 ogma_bool int_tmr_unit_ms_flag, 595 ogma_uint16 int_tmr_cnt 596 ); 597 598 ogma_uint32 ogma_get_mac_irq_enable ( 599 ogma_handle_t ogma_handle 600 ); 601 602 603 ogma_uint32 ogma_get_mac_irq_status ( 604 ogma_handle_t ogma_handle, 605 ogma_bool mask_flag 606 ); 607 608 #define ogma_get_mac_irq_status_non_clear(ogma_handle,mask_flag) \ 609 ogma_get_mac_irq_status(ogma_handle,mask_flag) 610 611 612 ogma_err_t ogma_clear_mac_irq_status ( 613 ogma_handle_t ogma_handle, 614 ogma_uint32 value 615 ); 616 617 ogma_err_t ogma_enable_mac_irq ( 618 ogma_handle_t ogma_handle, 619 ogma_uint32 irq_factor 620 ); 621 622 ogma_err_t ogma_disable_mac_irq ( 623 ogma_handle_t ogma_handle, 624 ogma_uint32 irq_factor 625 ); 626 627 #ifdef OGMA_CONFIG_REC_STAT 628 /** 629 * Get statistics information. 630 */ 631 ogma_err_t ogma_get_stat_info ( 632 ogma_handle_t ogma_handle, 633 ogma_stat_info_t *stat_info_p, 634 ogma_bool clear_flag 635 ); 636 #endif /* OGMA_CONFIG_REC_STAT */ 637 638 ogma_err_t ogma_set_gmac_lpictrl_reg ( 639 ogma_handle_t ogma_handle, 640 ogma_uint32 value 641 ); 642 643 ogma_err_t ogma_get_gmac_lpictrl_reg ( 644 ogma_handle_t ogma_handle, 645 ogma_uint32 *value_p 646 ); 647 648 ogma_err_t ogma_set_gmac_lpitimer_reg ( 649 ogma_handle_t ogma_handle, 650 ogma_uint16 ls_timer_ms, 651 ogma_uint16 tw_timer_ms 652 ); 653 654 ogma_err_t ogma_get_gmac_lpitimer_reg ( 655 ogma_handle_t ogma_handle, 656 ogma_uint16 *ls_timer_ms_p, 657 ogma_uint16 *tw_timer_ms_p 658 ); 659 660 void ogma_set_phy_mmd_reg ( 661 ogma_handle_t ogma_handle, 662 ogma_uint8 dev_addr, 663 ogma_uint16 reg_addr, 664 ogma_uint16 value 665 ); 666 667 ogma_uint16 ogma_get_phy_mmd_reg ( 668 ogma_handle_t ogma_handle, 669 ogma_uint8 dev_addr, 670 ogma_uint16 reg_addr 671 ); 672 673 ogma_err_t ogma_get_phy_link_status ( 674 ogma_handle_t ogma_handle, 675 ogma_phy_link_status_t *phy_link_status_p 676 ); 677 678 ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_enable ( 679 ogma_handle_t ogma_handle 680 ); 681 682 ogma_gmac_int_sbd_regs_t ogma_get_gmac_int_sbd_irq_status ( 683 ogma_handle_t ogma_handle, 684 ogma_bool mask_flag 685 ); 686 687 #define ogma_get_gmac_int_sbd_irq_status_non_clear(ogma_handle,mask_flag) \ 688 ogma_get_gmac_int_sbd_irq_status(ogma_handle,mask_flag) 689 690 ogma_err_t ogma_clear_gmac_int_sbd_irq_status ( 691 ogma_handle_t ogma_handle, 692 ogma_gmac_int_sbd_regs_t int_sbd_regs 693 ); 694 695 ogma_err_t ogma_enable_gmac_int_sbd_irq ( 696 ogma_handle_t ogma_handle, 697 ogma_gmac_int_sbd_regs_t int_sbd_regs 698 ); 699 700 ogma_err_t ogma_disable_gmac_int_sbd_irq ( 701 ogma_handle_t ogma_handle, 702 ogma_gmac_int_sbd_regs_t int_sbd_regs 703 ); 704 705 ogma_err_t ogma_get_gmac_rgmii_status_reg ( 706 ogma_handle_t ogma_handle, 707 ogma_uint32 *value_p 708 ); 709 710 #ifdef OGMA_CONFIG_USE_READ_GMAC_STAT 711 ogma_err_t ogma_read_gmac_stat ( 712 ogma_handle_t ogma_handle, 713 ogma_uint32 *value_p, 714 ogma_bool reset_flag 715 ); 716 #endif /* OGMA_CONFIG_USE_READ_GMAC_STAT */ 717 718 ogma_err_t ogma_reset_gmac_stat ( 719 ogma_handle_t ogma_handle 720 ); 721 722 /************************** 723 *************************** 724 ***************************/ 725 726 #endif /* OGMA_API_H*/ 727