/dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/cpu/z8000/ |
H A D | z8000ops.c | 1911 GET_BIT(OP0); in Z22_ddN0_imm4() 1933 GET_BIT(OP0); in Z23_ddN0_imm4() 1955 GET_BIT(OP0); in Z24_ddN0_imm4() 1977 GET_BIT(OP0); in Z25_ddN0_imm4() 1999 GET_BIT(OP0); in Z26_ddN0_imm4() 2021 GET_BIT(OP0); in Z27_ddN0_imm4() 3904 GET_BIT(OP0); in Z62_0000_imm4_addr() 3915 GET_BIT(OP0); in Z62_ddN0_imm4_addr() 3928 GET_BIT(OP0); in Z63_0000_imm4_addr() 3939 GET_BIT(OP0); in Z63_ddN0_imm4_addr() [all …]
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/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/z8000/ |
H A D | z8000ops.c | 1909 GET_BIT(OP0); in Z22_ddN0_imm4() 1931 GET_BIT(OP0); in Z23_ddN0_imm4() 1953 GET_BIT(OP0); in Z24_ddN0_imm4() 1975 GET_BIT(OP0); in Z25_ddN0_imm4() 1997 GET_BIT(OP0); in Z26_ddN0_imm4() 2019 GET_BIT(OP0); in Z27_ddN0_imm4() 3902 GET_BIT(OP0); in Z62_0000_imm4_addr() 3913 GET_BIT(OP0); in Z62_ddN0_imm4_addr() 3926 GET_BIT(OP0); in Z63_0000_imm4_addr() 3937 GET_BIT(OP0); in Z63_ddN0_imm4_addr() [all …]
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/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/z8000/ |
H A D | z8000ops.c | 1909 GET_BIT(OP0); in Z22_ddN0_imm4() 1931 GET_BIT(OP0); in Z23_ddN0_imm4() 1953 GET_BIT(OP0); in Z24_ddN0_imm4() 1975 GET_BIT(OP0); in Z25_ddN0_imm4() 1997 GET_BIT(OP0); in Z26_ddN0_imm4() 2019 GET_BIT(OP0); in Z27_ddN0_imm4() 3902 GET_BIT(OP0); in Z62_0000_imm4_addr() 3913 GET_BIT(OP0); in Z62_ddN0_imm4_addr() 3926 GET_BIT(OP0); in Z63_0000_imm4_addr() 3937 GET_BIT(OP0); in Z63_ddN0_imm4_addr() [all …]
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/z8000/ |
H A D | z8000ops.hxx | 2099 GET_BIT(OP0); in Z22_ddN0_imm4() 2123 GET_BIT(OP0); in Z23_ddN0_imm4() 2147 GET_BIT(OP0); in Z24_ddN0_imm4() 2171 GET_BIT(OP0); in Z25_ddN0_imm4() 2195 GET_BIT(OP0); in Z26_ddN0_imm4() 2217 GET_BIT(OP0); in Z27_ddN0_imm4() 4148 GET_BIT(OP0); in Z62_0000_imm4_addr() 4159 GET_BIT(OP0); in Z62_ddN0_imm4_addr() 4172 GET_BIT(OP0); in Z63_0000_imm4_addr() 4183 GET_BIT(OP0); in Z63_ddN0_imm4_addr() [all …]
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/z8000/ |
H A D | z8000ops.hxx | 2099 GET_BIT(OP0); in Z22_ddN0_imm4() 2123 GET_BIT(OP0); in Z23_ddN0_imm4() 2147 GET_BIT(OP0); in Z24_ddN0_imm4() 2171 GET_BIT(OP0); in Z25_ddN0_imm4() 2195 GET_BIT(OP0); in Z26_ddN0_imm4() 2217 GET_BIT(OP0); in Z27_ddN0_imm4() 4148 GET_BIT(OP0); in Z62_0000_imm4_addr() 4159 GET_BIT(OP0); in Z62_ddN0_imm4_addr() 4172 GET_BIT(OP0); in Z63_0000_imm4_addr() 4183 GET_BIT(OP0); in Z63_ddN0_imm4_addr() [all …]
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/dports/math/openblas/OpenBLAS-0.3.18/kernel/mips/ |
H A D | cgemv_t_msa.c | 31 #undef OP0 37 #define OP0 -= macro 41 #define OP0 += macro 47 #define OP0 += macro 51 #define OP0 -= macro 271 res0r OP0 alphai * temp0i; \ 273 res1r OP0 alphai * temp1i; \ 275 res2r OP0 alphai * temp2i; \ 277 res3r OP0 alphai * temp3i; \ 306 res0r OP0 alphai * temp0i; \ [all …]
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H A D | caxpy_msa.c | 32 #define OP0 += macro 36 #define OP0 -= macro 108 y0i OP0 dar_vec * x0i; in CNAME() 109 y1i OP0 dar_vec * x1i; in CNAME() 110 y2i OP0 dar_vec * x2i; in CNAME() 111 y3i OP0 dar_vec * x3i; in CNAME() 246 y0i OP0 dar_vec * x0i; in CNAME() 390 yd1 OP0 da_r * xd1; in CNAME() 391 yd3 OP0 da_r * xd3; in CNAME() 392 yd5 OP0 da_r * xd5; in CNAME() [all …]
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H A D | zaxpy_msa.c | 32 #define OP0 += macro 36 #define OP0 -= macro 107 y0i OP0 dar_vec * x0i; in CNAME() 108 y1i OP0 dar_vec * x1i; in CNAME() 109 y2i OP0 dar_vec * x2i; in CNAME() 110 y3i OP0 dar_vec * x3i; in CNAME() 173 yd1 OP0 da_r * xd1; in CNAME() 216 y0i OP0 dar_vec * x0i; in CNAME() 217 y1i OP0 dar_vec * x1i; in CNAME() 218 y2i OP0 dar_vec * x2i; in CNAME() [all …]
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H A D | zgemv_n_msa.c | 31 #undef OP0 47 #define OP0 -= macro 51 #define OP0 += macro 57 #define OP0 += macro 61 #define OP0 -= macro 154 res0 OP0 temp0_i * pa0[k + 1]; \ 156 res0 OP0 temp1_i * pa1[k + 1]; \ 158 res0 OP0 temp2_i * pa2[k + 1]; \ 160 res0 OP0 temp3_i * pa3[k + 1]; \ 227 res0 OP0 temp0_i * pa0[k + 1]; \ [all …]
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H A D | zgemv_t_msa.c | 31 #undef OP0 39 #define OP0 -= macro 43 #define OP0 += macro 49 #define OP0 += macro 53 #define OP0 -= macro 70 tp0r OP0 src0i * x0i; \ 75 tp0r OP0 src2i * x2i; \ 80 tp0r OP0 src1i * x1i; \ 85 tp0r OP0 src3i * x3i; \ 127 res0r OP0 alphai * temp0i; \ [all …]
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H A D | cgemv_n_msa.c | 31 #undef OP0 47 #define OP0 -= macro 51 #define OP0 += macro 57 #define OP0 += macro 61 #define OP0 -= macro 154 res0 OP0 temp0_i * pa0[k + 1]; \ 156 res0 OP0 temp1_i * pa1[k + 1]; \ 158 res0 OP0 temp2_i * pa2[k + 1]; \ 160 res0 OP0 temp3_i * pa3[k + 1]; \ 244 res0 OP0 temp_i * pa0[k + 1]; \ [all …]
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H A D | cgemm_kernel_8x4_msa.c | 215 #define CGEMM_KERNEL_2X4(OP0, OP1, OP2, OP3, OP4) \ argument 222 res0 OP0## = a0_r * b0_r; \ 229 res2 OP0## = a1_r * b0_r; \ 237 res4 OP0## = a0_r * b1_r; \ 242 res6 OP0## = a1_r * b1_r; \ 250 res8 OP0## = a0_r * b2_r; \ 255 res10 OP0## = a1_r * b2_r; \ 263 res12 OP0## = a0_r * b3_r; \ 268 res14 OP0## = a1_r * b3_r; \ 274 #define CGEMM_KERNEL_2X2(OP0, OP1, OP2, OP3, OP4) \ argument [all …]
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H A D | zgemm_kernel_4x4_msa.c | 31 #define ZGEMM_KERNEL_4X4_MSA(OP0, OP1, OP2, OP3, OP4) \ argument 41 res0_r OP0## = src_a0r * src_br; \ 46 res1_r OP0## = src_a1r * src_br; \ 53 res2_r OP0## = src_a0r * src_br; \ 58 res3_r OP0## = src_a1r * src_br; \ 65 res4_r OP0## = src_a0r * src_br; \ 70 res5_r OP0## = src_a1r * src_br; \ 179 #define ZGEMM_KERNEL_2X2_MSA(OP0, OP1, OP2, OP3, OP4) \ argument 188 res0_r OP0## = src_a0r * src_br; \ 252 #define ZGEMM_KERNEL_1X1(OP0, OP1, OP2, OP3, OP4) \ argument [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | subtract-from-one-hand-of-select.ll | 15 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]] 25 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]] 38 ; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]] 53 ; CHECK-NEXT: [[O:%.*]] = select i1 [[C:%.*]], i8 [[OP0:%.*]], i8 [[FALSEVAL:%.*]] 55 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0]], [[O]] 69 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[OP0:%.*]], [[O]]
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