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Searched refs:OPCODE1 (Results 1 – 25 of 33) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/arch/parisc/kernel/
H A Dunaligned.c46 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
52 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
53 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
54 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
60 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
61 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
68 #define OPCODE_STH OPCODE1(0x03,1,0x9)
69 #define OPCODE_STW OPCODE1(0x03,1,0xa)
70 #define OPCODE_STD OPCODE1(0x03,1,0xb)
73 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/parisc/kernel/
H A Dunaligned.c46 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
52 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
53 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
54 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
60 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
61 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
68 #define OPCODE_STH OPCODE1(0x03,1,0x9)
69 #define OPCODE_STW OPCODE1(0x03,1,0xa)
70 #define OPCODE_STD OPCODE1(0x03,1,0xb)
73 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/parisc/kernel/
H A Dunaligned.c46 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
52 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
53 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
54 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
60 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
61 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
68 #define OPCODE_STH OPCODE1(0x03,1,0x9)
69 #define OPCODE_STW OPCODE1(0x03,1,0xa)
70 #define OPCODE_STD OPCODE1(0x03,1,0xb)
73 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td23 class OPCODE1<bits<1> Val> {
27 def OPCODE_SC_D : OPCODE1<0b0>;
28 def OPCODE_SC_E : OPCODE1<0b1>;
40 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td23 class OPCODE1<bits<1> Val> {
27 def OPCODE_SC_D : OPCODE1<0b0>;
28 def OPCODE_SC_E : OPCODE1<0b1>;
40 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Mips/
H A DMipsMTInstrFormats.td22 class OPCODE1<bits<1> Val> {
26 def OPCODE_SC_D : OPCODE1<0b0>;
27 def OPCODE_SC_E : OPCODE1<0b1>;
39 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/x86/kernel/
H A Duprobes.c41 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) macro
299 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) in uprobe_init_insn()
718 u8 opc1 = OPCODE1(insn); in branch_setup_xol_ops()
767 u8 opc1 = OPCODE1(insn), reg_offset = 0; in push_setup_xol_ops()
874 switch (OPCODE1(&insn)) { in arch_uprobe_analyze_insn()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/x86/kernel/
H A Duprobes.c41 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) macro
299 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) in uprobe_init_insn()
718 u8 opc1 = OPCODE1(insn); in branch_setup_xol_ops()
767 u8 opc1 = OPCODE1(insn), reg_offset = 0; in push_setup_xol_ops()
874 switch (OPCODE1(&insn)) { in arch_uprobe_analyze_insn()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/x86/kernel/
H A Duprobes.c41 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) macro
299 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) in uprobe_init_insn()
718 u8 opc1 = OPCODE1(insn); in branch_setup_xol_ops()
767 u8 opc1 = OPCODE1(insn), reg_offset = 0; in push_setup_xol_ops()
874 switch (OPCODE1(&insn)) { in arch_uprobe_analyze_insn()
/dports/lang/v8/v8-9.6.180.12/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc3100 #define VISIT_EXT_MUL(OPCODE1, OPCODE2) \ argument
3101 void InstructionSelector::Visit##OPCODE1##ExtMulLow##OPCODE2(Node* node) { \
3104 void InstructionSelector::Visit##OPCODE1##ExtMulHigh##OPCODE2(Node* node) { \
/dports/lang/v8/v8-9.6.180.12/src/compiler/backend/loong64/
H A Dinstruction-selector-loong64.cc3045 #define VISIT_EXT_MUL(OPCODE1, OPCODE2) \ argument
3046 void InstructionSelector::Visit##OPCODE1##ExtMulLow##OPCODE2(Node* node) {} \
3047 void InstructionSelector::Visit##OPCODE1##ExtMulHigh##OPCODE2(Node* node) {}

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