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Searched refs:OPC_JALR (Results 1 – 25 of 86) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/riscv/include/asm/
H A Dmodule.h59 #define OPC_JALR 0x0067 macro
85 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/riscv/include/asm/
H A Dmodule.h59 #define OPC_JALR 0x0067 macro
85 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/riscv/include/asm/
H A Dmodule.h59 #define OPC_JALR 0x0067 macro
85 OPC_JALR | (REG_T1 << 15) in emit_plt_entry()
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/riscv/
H A Dtcg-target.inc.c217 OPC_JALR = 0x67, enumerator
881 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); in tcg_out_call_int()
889 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); in tcg_out_call_int()
1307 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); in tcg_out_op()
1312 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); in tcg_out_op()
1826 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); in tcg_target_qemu_prologue()
1840 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); in tcg_target_qemu_prologue()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/riscv/
H A Dtcg-target.inc.c217 OPC_JALR = 0x67, enumerator
881 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); in tcg_out_call_int()
889 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); in tcg_out_call_int()
1307 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); in tcg_out_op()
1312 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); in tcg_out_op()
1826 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); in tcg_target_qemu_prologue()
1840 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); in tcg_target_qemu_prologue()
/dports/emulators/qemu42/qemu-4.2.1/tcg/riscv/
H A Dtcg-target.inc.c217 OPC_JALR = 0x67, enumerator
881 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); in tcg_out_call_int()
889 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); in tcg_out_call_int()
1307 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); in tcg_out_op()
1312 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); in tcg_out_op()
1826 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); in tcg_target_qemu_prologue()
1840 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); in tcg_target_qemu_prologue()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/riscv/
H A Dtcg-target.inc.c217 OPC_JALR = 0x67, enumerator
881 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); in tcg_out_call_int()
889 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); in tcg_out_call_int()
1307 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); in tcg_out_op()
1312 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); in tcg_out_op()
1826 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); in tcg_target_qemu_prologue()
1840 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); in tcg_target_qemu_prologue()
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/tcg/mips/
H A Dtcg-target.c297 OPC_JALR = OPC_SPECIAL | 0x09, enumerator
698 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); in tcg_out_qemu_ld()
910 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); in tcg_out_qemu_st()
991 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, args[0], 0); in tcg_out_op()
/dports/emulators/qemu5/qemu-5.2.0/tcg/riscv/
H A Dtcg-target.c.inc215 OPC_JALR = 0x67,
877 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
885 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
1303 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1308 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1822 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1836 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/riscv/
H A Dtcg-target.c.inc187 OPC_JALR = 0x67,
807 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
815 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
1233 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1238 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1713 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1727 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
/dports/emulators/qemu/qemu-6.2.0/tcg/riscv/
H A Dtcg-target.c.inc187 OPC_JALR = 0x67,
807 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
815 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
1233 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1238 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1713 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1727 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
/dports/emulators/qemu60/qemu-6.0.0/tcg/riscv/
H A Dtcg-target.c.inc189 OPC_JALR = 0x67,
809 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
817 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
1239 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1244 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1719 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1733 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/RISCV/
H A DRISCVInstrFormats.td76 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/RISCV/
H A DRISCVInstrFormats.td75 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/tcg/
H A Dmicromips_translate.c.inc808 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4);
813 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2);
935 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
1195 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
1198 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4);
1205 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
/dports/emulators/qemu/qemu-6.2.0/target/mips/tcg/
H A Dmicromips_translate.c.inc808 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 4);
813 gen_compute_branch(ctx, OPC_JALR, 2, ctx->opcode & 0x1f, 31, 0, 2);
935 gen_compute_branch(ctx, OPC_JALR, 2, (ctx->opcode >> 5) & 0x1f,
1195 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0);
1198 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 4);
1205 gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2);
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormats.td75 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/RISCV/
H A DRISCVInstrFormats.td75 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A DRISCVInstrFormats.td75 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/RISCV/
H A DRISCVInstrFormats.td75 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrFormats.td111 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/RISCV/
H A DRISCVInstrFormats.td91 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/RISCV/
H A DRISCVInstrFormats.td89 def OPC_JALR : RISCVOpcode<0b1100111>;
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/mips/
H A Dtcg-target.inc.c315 OPC_JALR = OPC_SPECIAL | 011, enumerator
397 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
1098 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); in tcg_out_call_int()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/mips/
H A Dtcg-target.inc.c315 OPC_JALR = OPC_SPECIAL | 011, enumerator
397 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
1098 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); in tcg_out_call_int()

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