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Searched refs:OP_MASK_RT (Results 1 – 25 of 37) sorted by relevance

12

/dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/
H A Dmips-dis.c127 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
181 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
189 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
190 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
196 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
259 (l >> OP_SH_RT) & OP_MASK_RT);
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/
H A Dmips-dis.c867 OP_MASK_RT]); in print_insn_args()
875 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
1008 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1068 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) { in print_insn_args()
1075 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1076 } else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) { in print_insn_args()
1082 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1154 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Dmips-dis.c777 OP_MASK_RT]); in print_insn_args()
785 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
909 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
963 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
971 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
972 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
978 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1049 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Dmips-dis.c924 OP_MASK_RT]); in print_insn_args()
932 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
1120 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1178 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
1186 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1187 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
1193 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1265 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Dmips-dis.c796 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
850 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
858 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
859 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
865 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
935 (l >> OP_SH_RT) & OP_MASK_RT);
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-dis.c785 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
839 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
847 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
848 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
854 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
924 (l >> OP_SH_RT) & OP_MASK_RT);
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Dmips-dis.c785 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
839 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
847 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
848 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
854 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
924 (l >> OP_SH_RT) & OP_MASK_RT);
/dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/opcode/
H A Dmips.h74 #define OP_MASK_RT 0x1f macro
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/include/opcode/
H A Dmips.h74 #define OP_MASK_RT 0x1f
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/include/opcode/
H A Dmips.h75 #define OP_MASK_RT 0x1f macro
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/include/opcode/
H A Dmips.h74 #define OP_MASK_RT 0x1f macro
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/include/opcode/
H A Dmips.h75 #define OP_MASK_RT 0x1f macro
/dports/devel/djgpp-binutils/binutils-2.17/include/opcode/
H A Dmips.h75 #define OP_MASK_RT 0x1f macro
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4306 delta |= ~OP_MASK_RT; in print_insn_args()
4468 OP_MASK_RT]); in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4296 delta |= ~OP_MASK_RT; in print_insn_args()
4458 OP_MASK_RT]); in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4306 delta |= ~OP_MASK_RT; in print_insn_args()
4468 OP_MASK_RT]); in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4296 delta |= ~OP_MASK_RT; in print_insn_args()
4458 OP_MASK_RT]); in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4306 delta |= ~OP_MASK_RT; in print_insn_args()
4468 OP_MASK_RT]); in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4296 delta |= ~OP_MASK_RT; in print_insn_args()
4458 OP_MASK_RT]); in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f in HostBreakpoint()
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT);
4306 delta |= ~OP_MASK_RT;
4468 OP_MASK_RT]);
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4306 delta |= ~OP_MASK_RT; in print_insn_args()
4468 OP_MASK_RT]); in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Dmips.c95 #define OP_MASK_RT 0x1f macro
4531 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4533 delta |= ~OP_MASK_RT; in print_insn_args()
4746 OP_MASK_RT]); in print_insn_args()
4754 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4773 OP_MASK_RT); in print_insn_args()
4963 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
5027 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
5035 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
5036 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/include/opcode/
H A Dmips.h76 #define OP_MASK_RT 0x1f macro
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Dmips-dis.c94 #define OP_MASK_RT 0x1f macro
3550 OP_MASK_RT]); in print_insn_args()
3558 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
3687 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
3745 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
3753 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
3754 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
3760 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
3831 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
/dports/devel/gdb761/gdb-7.6.1/include/opcode/
H A Dmips.h78 #define OP_MASK_RT 0x1f macro

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