| /dports/converters/wkhtmltopdf/qt-5db36ec/src/3rdparty/webkit/Source/JavaScriptCore/assembler/ |
| H A D | MIPSAssembler.h | 160 OP_SH_RT = 16, enumerator
224 emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff)); in lui()
236 | (rt << OP_SH_RT)); in addu()
242 | (rt << OP_SH_RT)); in subu()
269 | (rt << OP_SH_RT)); in mul()
279 | (rt << OP_SH_RT)); in andInsn()
291 | (rt << OP_SH_RT)); in nor()
297 | (rt << OP_SH_RT)); in orInsn()
309 | (rt << OP_SH_RT)); in xorInsn()
321 | (rt << OP_SH_RT)); in slt()
[all …]
|
| /dports/x11-toolkits/qt5-declarative-test/kde-qtdeclarative-5.15.2p41/src/3rdparty/masm/assembler/ |
| H A D | MIPSAssembler.h | 163 OP_SH_RT = 16, enumerator
227 emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff)); in lui()
232 emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in addiu()
247 emitInst(0x00000018 | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in mult()
252 emitInst(0x0000001a | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in div()
282 emitInst(0x30000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in andi()
297 emitInst(0x34000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in ori()
511 emitInst(0x44800000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mtc1()
517 emitInst(0x44e00000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mthc1()
523 emitInst(0x44000000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mfc1()
[all …]
|
| /dports/x11-toolkits/qt5-declarative/kde-qtdeclarative-5.15.2p41/src/3rdparty/masm/assembler/ |
| H A D | MIPSAssembler.h | 163 OP_SH_RT = 16, enumerator
227 emitInst(0x3c000000 | (rt << OP_SH_RT) | (imm & 0xffff)); in lui()
232 emitInst(0x24000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in addiu()
247 emitInst(0x00000018 | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in mult()
252 emitInst(0x0000001a | (rs << OP_SH_RS) | (rt << OP_SH_RT)); in div()
282 emitInst(0x30000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in andi()
297 emitInst(0x34000000 | (rt << OP_SH_RT) | (rs << OP_SH_RS) | (imm & 0xffff)); in ori()
511 emitInst(0x44800000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mtc1()
517 emitInst(0x44e00000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mthc1()
523 emitInst(0x44000000 | (fs << OP_SH_FS) | (rt << OP_SH_RT)); in mfc1()
[all …]
|
| /dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/ |
| H A D | mips-dis.c | 127 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
181 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
189 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
190 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
196 reg_names[(l >> OP_SH_RT) & OP_MASK_RT]);
259 (l >> OP_SH_RT) & OP_MASK_RT);
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/mips/gnu/ |
| H A D | mips-dis.c | 866 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
875 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
1008 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1068 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) { in print_insn_args()
1075 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1076 } else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) { in print_insn_args()
1082 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1154 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
|
| /dports/devel/djgpp-binutils/binutils-2.17/opcodes/ |
| H A D | mips-dis.c | 776 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
785 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
909 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
963 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
971 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
972 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
978 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1049 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
|
| /dports/devel/avr-gdb/gdb-7.3.1/opcodes/ |
| H A D | mips-dis.c | 923 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
932 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
1120 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1178 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
1186 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1187 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
1193 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
1265 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
|
| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/ |
| H A D | mips-dis.c | 796 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
850 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
858 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
859 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
865 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
935 (l >> OP_SH_RT) & OP_MASK_RT);
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
| H A D | mips-dis.c | 785 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
839 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
847 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
848 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
854 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
924 (l >> OP_SH_RT) & OP_MASK_RT);
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/ |
| H A D | mips-dis.c | 785 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
839 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
847 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
848 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
854 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
924 (l >> OP_SH_RT) & OP_MASK_RT);
|
| /dports/emulators/vmips/vmips-1.5.1/libopcodes_mips/opcode/ |
| H A D | mips.h | 75 #define OP_SH_RT 16 macro
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
| H A D | mips.h | 75 #define OP_SH_RT 16
|
| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/include/opcode/ |
| H A D | mips.h | 76 #define OP_SH_RT 16 macro
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
| H A D | mips.h | 75 #define OP_SH_RT 16 macro
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/include/opcode/ |
| H A D | mips.h | 76 #define OP_SH_RT 16 macro
|
| /dports/devel/djgpp-binutils/binutils-2.17/include/opcode/ |
| H A D | mips.h | 76 #define OP_SH_RT 16 macro
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/gas/config/ |
| H A D | tc-mips.c | 1473 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1677 ((prev_insn.insn_opcode >> OP_SH_RT)
2418 ((prev_insn.insn_opcode >> OP_SH_RT)
2464 && (((prev_insn.insn_opcode >> OP_SH_RT)
2513 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
3069 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3091 insn.insn_opcode |= tmp << OP_SH_RT;
8194 ip->insn_opcode |= lastregno << OP_SH_RT;
8612 ip->insn_opcode |= regno << OP_SH_RT;
8617 ip->insn_opcode |= regno << OP_SH_RT;
[all …]
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/gas/config/ |
| H A D | tc-mips.c | 1473 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) in insn_uses_reg()
1677 ((prev_insn.insn_opcode >> OP_SH_RT) in append_insn()
2418 ((prev_insn.insn_opcode >> OP_SH_RT) in append_insn()
2464 && (((prev_insn.insn_opcode >> OP_SH_RT) in append_insn()
2513 ((prev_prev_insn.insn_opcode >> OP_SH_RT) in append_insn()
3069 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; in macro_build()
3091 insn.insn_opcode |= tmp << OP_SH_RT; in macro_build()
8194 ip->insn_opcode |= lastregno << OP_SH_RT; in mips_ip()
8612 ip->insn_opcode |= regno << OP_SH_RT; in mips_ip()
8617 ip->insn_opcode |= regno << OP_SH_RT; in mips_ip()
[all …]
|
| /dports/devel/avr-gdb/gdb-7.3.1/include/opcode/ |
| H A D | mips.h | 77 #define OP_SH_RT 16 macro
|
| /dports/emulators/qemu/qemu-6.2.0/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4467 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4782 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4457 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4772 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|
| /dports/emulators/qemu60/qemu-6.0.0/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4467 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4782 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4457 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4772 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4304 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4467 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4476 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4637 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4696 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4704 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4705 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4711 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4782 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/disas/ |
| H A D | mips.c | 96 #define OP_SH_RT 16 macro
4294 delta = ((l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
4457 mips_cp0_names[(l >> OP_SH_RT) & in print_insn_args()
4466 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; in print_insn_args()
4627 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4686 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) in print_insn_args()
4694 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4695 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) in print_insn_args()
4701 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); in print_insn_args()
4772 (l >> OP_SH_RT) & OP_MASK_RT); in print_insn_args()
[all …]
|