Searched refs:OP_SVE_VRU_BHSD (Results 1 – 9 of 9) sorted by relevance
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-2016 | 831 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
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H A D | aarch64-tbl.h | 1829 #define OP_SVE_VRU_BHSD \ macro 4178 …"index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
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/dports/devel/gdb/gdb-11.1/opcodes/ |
H A D | ChangeLog-2016 | 831 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
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H A D | aarch64-tbl.h | 1829 #define OP_SVE_VRU_BHSD \ macro 4178 …"index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
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/dports/devel/gnulibiberty/binutils-2.37/opcodes/ |
H A D | ChangeLog-2016 | 831 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
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H A D | aarch64-tbl.h | 1829 #define OP_SVE_VRU_BHSD \ macro 4178 …"index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
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/dports/devel/binutils/binutils-2.37/opcodes/ |
H A D | ChangeLog-2016 | 831 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
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H A D | aarch64-tbl.h | 1829 #define OP_SVE_VRU_BHSD \ macro 4178 …"index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
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/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/arm/aarch64/ |
H A D | aarch64-tbl.h | 1728 #define OP_SVE_VRU_BHSD \ macro 3766 …"index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
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