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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/InstCombine/
H A Dmasked-merge-and-of-ors.ll21 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y:%.*]], [[M]]
22 ; CHECK-NEXT: [[RET:%.*]] = and i32 [[OR]], [[OR1]]
145 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
177 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
209 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[Y]], [[M]]
299 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
336 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
356 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
376 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
410 ; CHECK-NEXT: call void @use32(i32 [[OR1]])
[all …]
/dports/cad/calculix-ccx/CalculiX/ccx_2.18/test/
H A Dsens_freq_orien.dat.ref43 1 OR1 Rx
44 2 OR1 Ry
45 3 OR1 Rz
51 OR1 Rx 0.1406E+04
52 OR1 Ry -0.1772E+04
53 OR1 Rz 0.8690E+04
59 OR1 Rx -0.9147E+03
60 OR1 Ry -0.8601E+04
61 OR1 Rz -0.7180E+04
67 OR1 Rx -0.3876E-02
[all …]
H A Dgreen2.dat.ref6 1 OR1 Rx
7 2 OR1 Ry
8 3 OR1 Rz
H A Dsens_disp_orien.dat.ref6 1 OR1 Rx
7 2 OR1 Ry
8 3 OR1 Rz
H A Dcontact10.dat.ref6 1 OR1 Rx
7 2 OR1 Ry
8 3 OR1 Rz
H A Dsens_disp_orien_nlgeom.dat.ref6 1 OR1 Rx
7 2 OR1 Ry
8 3 OR1 Rz
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-or.mir255 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
275 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
295 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
315 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
366 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
395 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
422 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
452 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
484 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
511 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-or.mir255 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
275 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
295 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
315 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
366 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
395 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
422 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
452 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
484 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
511 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-or.mir250 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
270 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
290 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
310 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
361 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
390 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
417 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
447 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
479 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
506 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-or.mir255 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
275 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
295 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
315 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
366 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
395 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
422 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
452 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
484 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
511 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-or.mir255 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
275 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
295 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
315 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
366 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
395 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
422 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
452 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
484 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
511 ; CHECK: [[OR1:%[0-9]+]]:vgpr(s32) = G_OR [[UV1]], [[UV3]]
[all …]

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