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Searched refs:ORION5X_REG_PCIE_BASE (Results 1 – 25 of 140) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-orion5x/
H A Dcpu.h111 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
112 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h150 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
151 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)

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