OVLC1_EN (reference) in projects: dports

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Searched refs:OVLC1_EN (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 439 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 464 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 468 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 476 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 480 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 481 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 482 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/display/
H A D	pxa2xx_lcd.c	160 #define OVLC1_EN (1 << 31) macro 437 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 462 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 466 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 474 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 478 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 479 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 480 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu5/qemu-5.2.0/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 441 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 466 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 470 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 478 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 482 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 483 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 484 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 439 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 464 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 468 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 476 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 480 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 481 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 482 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/display/
H A D	pxa2xx_lcd.c	`162 #define OVLC1_EN (1 << 31) in init() 439 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); 464 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) 468 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); 476 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) 480 s->dma_ch[2].up = !!(value & OVLC1_EN); 481 s->dma_ch[3].up = !!(value & OVLC1_EN); 482 s->dma_ch[4].up = !!(value & OVLC1_EN);`
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 439 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 464 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 468 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 476 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) in pxa2xx_lcdc_write() 480 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 481 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 482 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu/qemu-6.2.0/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 870 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 895 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 899 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 907 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 911 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 912 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 913 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu60/qemu-6.0.0/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 870 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 895 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 899 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 907 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 911 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 912 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 913 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/display/
H A D	pxa2xx_lcd.c	162 #define OVLC1_EN (1 << 31) macro 870 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) \|\| (value & LCCR0_SDS); in pxa2xx_lcdc_write() 895 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 899 s->dma_ch[1].up = (value & OVLC1_EN) \|\| (s->control[0] & LCCR0_SDS); in pxa2xx_lcdc_write() 907 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) { in pxa2xx_lcdc_write() 911 s->dma_ch[2].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 912 s->dma_ch[3].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write() 913 s->dma_ch[4].up = !!(value & OVLC1_EN); in pxa2xx_lcdc_write()